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38K2 Datasheet, PDF (81/151 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER | |||
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38K2 Group
EXB Operation Timing Diagram
(1) CPU Channel Receiving Operation
CPU channel receiving operation is shown bellow.
â
Address ExA0
Chip select ExCS
Read ExRD
Write ExWR
Data DQ0 to DQ7
â
A0 = â1â
CS = â0â
â
#0
â
A0 = â1â
CS = â0â
#1
Internal clock Ï
Interrupt request ExINT
[RxB_RDY]
Receive buffer full bit RXB_FULL
RxB_RDY
RxB_RDY
Receive buffer RXBUF
#0
#1
Transmit buffer TXBUF
â
CPU channel receive enable bit
RXB_ENB
Receive buffer read
â
<Initial setting>
External I/O configuration register
INT_CTR[3:1] (P33/ExINT pin control) = 0012 (RxB_RDY interrupt)
<Operation start>
EXB interrupt source enable register
RXB_ENB (CPU channel receive enable) = â1â (Receive buffer full interrupt enabled)
â Writing the command for enabling operation makes RXB_RDY assertion and the P33/ExINT pin goes to âLâ.
If the CPU channel receive enable bit (RXB_ENB) is â0â, both the receive buffer full bit (RXB_FULL) and the receive buffer ready signal (RxB_RDY) to an
external are inactive.
â When a write operation is performed from an external MCU bus in the condition of ExCS = âLâ and WxA0 = âHâ, it will result in as follows:
⢠The data is written into the receive buffer (RXBUF)
⢠Negation of the receive buffer ready signal (RxB_RDY) to an external is made
⢠The RXB_FULL interrupt is generated.
â When the CPU reads out the receive buffer (RXBUF) with an interrupt processing program, the receive buffer full bit (RXB_FULL) is cleared to â0â.
Fig. 122 CPU channel receiving operation
Rev.3.00 Oct 15, 2006 page 81 of 147
REJ03B0193-0300
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