RX113_16 Datasheet, PDF (87/131 Pages) Renesas Technology Corp – 32 MHz, 32-bit RX MCUs, 50 DMIPS, up to 512 Kbytes of flash memory

RX113 Group
5. Electrical Characteristics
Table 5.33 Timing of On-Chip Peripheral Modules (4)
Conditions: 2.7 V ≤ VCC = VCC_USB ≤ 3.6 V, 2.7 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, fPCLKB ≤ 32 MHz,
T_a = –40 to +105°C
Item
Symbol
Min.*¹
Max.
Unit
Test
Conditions
RIIC
(Standard mode,
SMBus)
SCL0 input cycle time
SCL0 input high pulse width
SCL0 input low pulse width
SCL0, SDA0 input rise time
SCL0, SDA0 input fall time
SCL0, SDA0 input spike pulse removal
time
t_SCL
t_SCLH
t_SCLL
t_Sr
t_Sf
t_SP
6 (12) × t_IICcyc + 1300
3 (6) × t_IICcyc + 300
3 (6) × t_IICcyc + 300
—
—
0
—
—
—
1000
300
1 (4) × t_IICcyc
ns Figure 5.49
ns
ns
ns
ns
ns
SDA0 input bus free time
t_BUF
3 (6) × t_IICcyc + 300
—
ns
START condition input hold time
t_STAH
t_IICcyc + 300
—
ns
Repeated START condition input setup t_STAS
time
1000
—
ns
RIIC
(Fast mode)
STOP condition input setup time
Data input setup time
Data input hold time
SCL0, SDA0 capacitive load
SCL0 input cycle time
SCL0 input high pulse width
SCL0 input low pulse width
SCL0, SDA0 input rise time
SCL0, SDA0 input fall time
SCL0, SDA0 input spike pulse removal
time
t_STOS
t_SDAS
t_SDAH
C_b
t_SCL
t_SCLH
t_SCLL
t_Sr
t_Sf
t_SP
1000
t_IICcyc + 50
0
—
6 (12) × t_IICcyc + 600
3 (6) × t_IICcyc + 300
3 (6) × t_IICcyc + 300
—*²
—*²
0
—
—
—
400
—
—
—
300
300
1 (4) × t_IICcyc
ns
ns
ns
pF
ns Figure 5.49
ns
ns
ns
ns
ns
SDA0 input bus free time
t_BUF
3 (6) × t_IICcyc + 300
—
ns
START condition input hold time
t_STAH
t_IICcyc + 300
—
ns
Repeated START condition input setup t_STAS
300
time
—
ns
STOP condition input setup time
Data input setup time
Data input hold time
SCL0, SDA0 capacitive load
t_STOS
t_SDAS
t_SDAH
C_b
300
t_IICcyc + 50
0
—
—
ns
—
ns
—
ns
400
pF
Note:
Note 1.
Note 2.
t_IICcyc: RIIC internal reference count clock (IICφ) cycle
The value in parentheses is used when the ICMR3.NF[1:0] bits are set to 11b while a digital filter is enabled with the ICFER.NFE
bit = 1.
The minimum tsr and tsf specifications for fast mode are not set.
R01DS0216EJ0110 Rev.1.10
Mar 31, 2016
Page 87 of 131