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RX113_16 Datasheet, PDF (85/131 Pages) Renesas Technology Corp – 32 MHz, 32-bit RX MCUs, 50 DMIPS, up to 512 Kbytes of flash memory | |||
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RX113 Group
5. Electrical Characteristics
Table 5.31 Timing of On-Chip Peripheral Modules (2)
Conditions: 1.8 V ⤠VCC = VCC_USB ⤠3.6 V, 1.8 V ⤠AVCC0 ⤠3.6 V, VSS = AVSS0 = VSS_USB = 0 V,
Ta = â40 to +105°C, C = 30 pF
Item
Symbol
Min.
Max.
Unit
Test
Conditions
RSPI RSPCK clock cycle
Master
Slave
tSPcyc
2
8
4096
4096
tPcyc*1 Figure 5.42
RSPCK clock
high pulse width
Master
tSPCKWH (tSPcyc â tSPCKr â
â
ns
tSPCKf)/2 â 3
Slave
(tSPcyc â tSPCKr â
â
tSPCKf)/2
RSPCK clock
low pulse width
Master
tSPCKWL (tSPcyc â tSPCKrâ
â
ns
tSPCKf)/2 â 3
Slave
(tSPcyc â tSPCKr â
â
tSPCKf)/2
RSPCK clock
rise/fall time
Output 2.7 V or above
1.8 V or above
tSPCKr,
â
tSPCKf
â
10
ns
15
Input
â
1
μs
Data input setup time Master 2.7 V or above
tSU
1.8 V or above
Slave
Data input hold time Master RSPCK set to a division
tH
ratio other than PCLKB
divided by 2
10
30
25 â tPcyc
tPcyc
â
ns Figure 5.43
â
to
Figure 5.48
â
â
ns
RSPCK set to PCLKB
tHF
0
â
divided by 2
SSL setup time
Slave
Master
SSL hold time
Slave
Master
Slave
Data output delay time Master 2.7 V or above
1.8 V or above
tH
tLEAD
tLAG
tOD
20 + 2 Ã tPcyc
â30 + N*2 Ã
tSPcyc
2
â30 + N*3 Ã
tSPcyc
2
â
â
â
â
ns
â
tPcyc
â
ns
â
tPcyc
14
ns
30
Data output hold time
Slave 2.7 V or above
1.8 V or above
Master 2.7 V or above
1.8 V or above
â
3 Ã tPcyc + 65
â
3 Ã tPcyc +105
tOH
0
â
ns
â20
â
Slave
0
â
Successive
transmission delay
time
MOSI and MISO rise/
fall time
Master
Slave
Output 2.7 V or above
1.8 V or above
Input
tTD
tSPcyc + 2 Ã tPcyc 8 Ã tSPcyc + 2 Ã
ns
tPcyc
4 Ã tPcyc
â
tDr, tDf
â
10
ns
â
20
â
1
μs
SSL rise/fall time
Output
Input
tSSLr,
â
tSSLf
â
20
ns
1
μs
Slave access time
2.7 V or above
1.8 V or above
tSA
â
â
6
tPcyc Figure 5.47,
7
Figure 5.48
Slave output release time
2.7 V or above
1.8 V or above
tREL
â
â
5
tPcyc
6
Note 1. tPcyc: PCLK cycle
Note 2. N: An integer from 1 to 8 that can be set by the RSPI clock delay register (SPCKD)
Note 3. N: An integer from 1 to 8 that can be set by the RSPI slave select negation delay register (SSLND)
R01DS0216EJ0110 Rev.1.10
Mar 31, 2016
Page 85 of 131
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