RX113_16 Datasheet, PDF (45/131 Pages) Renesas Technology Corp – 32 MHz, 32-bit RX MCUs, 50 DMIPS, up to 512 Kbytes of flash memory

RX113 Group
Table 4.1
List of I/O Registers (Address Order) (16/23)
Address
Module
Symbol
0008 B331h SCI12
0008 B332h SCI12
0008 B333h SCI12
0008 C000h PORT0
0008 C001h PORT1
0008 C002h PORT2
0008 C003h PORT3
0008 C004h PORT4
0008 C005h PORT5
0008 C009h PORT9
0008 C00Ah PORTA
0008 C00Bh PORTB
0008 C00Ch PORTC
0008 C00Dh PORTD
0008 C00Eh PORTE
0008 C00Fh PORTF
0008 C012h PORTJ
0008 C020h PORT0
0008 C021h PORT1
0008 C022h PORT2
0008 C023h PORT3
0008 C024h PORT4
0008 C025h PORT5
0008 C029h PORT9
0008 C02Ah PORTA
0008 C02Bh PORTB
0008 C02Ch PORTC
0008 C02Dh PORTD
0008 C02Eh PORTE
0008 C02Fh PORTF
0008 C032h PORTJ
0008 C040h PORT0
Timer Mode Register
Timer Prescaler Register
Timer Count Register
Port Direction Register
Port Direction Register
Port Direction Register
Port Direction Register
Port Direction Register
Port Direction Register
Port Direction Register
Port Direction Register
Port Direction Register
Port Direction Register
Port Direction Register
Port Direction Register
Port Direction Register
Port Direction Register
Port Output Data Register
Port Output Data Register
Port Output Data Register
Port Output Data Register
Port Output Data Register
Port Output Data Register
Port Output Data Register
Port Output Data Register
Port Output Data Register
Port Output Data Register
Port Output Data Register
Port Output Data Register
Port Output Data Register
Port Output Data Register
Port Input Data Register
Register Name
0008 C041h PORT1
Port Input Data Register
0008 C042h PORT2
Port Input Data Register
0008 C043h PORT3
Port Input Data Register
0008 C044h PORT4
Port Input Data Register
0008 C045h PORT5
Port Input Data Register
0008 C049h PORT9
Port Input Data Register
0008 C04Ah PORTA
Port Input Data Register
R01DS0216EJ0110 Rev.1.10
Mar 31, 2016
4. I/O Registers
Register
Symbol
TMR
TPRE
TCNT
PDR
PDR
PDR
PDR
PDR
PDR
PDR
PDR
PDR
PDR
PDR
PDR
PDR
PDR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
Number of
Bits
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Access
Size
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Number of Access
States
2 or 3 PCLKB
2 or 3 PCLKB
2 or 3 PCLKB
2 or 3 PCLKB
2 or 3 PCLKB
2 or 3 PCLKB
2 or 3 PCLKB
2 or 3 PCLKB
2 or 3 PCLKB
2 or 3 PCLKB
2 or 3 PCLKB
2 or 3 PCLKB
2 or 3 PCLKB
2 or 3 PCLKB
2 or 3 PCLKB
2 or 3 PCLKB
2 or 3 PCLKB
2 or 3 PCLKB
2 or 3 PCLKB
2 or 3 PCLKB
2 or 3 PCLKB
2 or 3 PCLKB
2 or 3 PCLKB
2 or 3 PCLKB
2 or 3 PCLKB
2 or 3 PCLKB
2 or 3 PCLKB
2 or 3 PCLKB
2 or 3 PCLKB
2 or 3 PCLKB
2 or 3 PCLKB
3 or 4 PCLKB cycles
when reading,
2 or 3 PCLKB cycles
when writing
3 or 4 PCLKB cycles
when reading,
2 or 3 PCLKB cycles
when writing
3 or 4 PCLKB cycles
when reading,
2 or 3 PCLKB cycles
when writing
3 or 4 PCLKB cycles
when reading,
2 or 3 PCLKB cycles
when writing
3 or 4 PCLKB cycles
when reading,
2 or 3 PCLKB cycles
when writing
3 or 4 PCLKB cycles
when reading,
2 or 3 PCLKB cycles
when writing
3 or 4 PCLKB cycles
when reading,
2 or 3 PCLKB cycles
when writing
3 or 4 PCLKB cycles
when reading,
2 or 3 PCLKB cycles
when writing
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