RX113_16 Datasheet, PDF (3/131 Pages) Renesas Technology Corp – 32 MHz, 32-bit RX MCUs, 50 DMIPS, up to 512 Kbytes of flash memory

RX113 Group
1. Overview
Table 1.1
Outline of Specifications (2/3)
Classification
DMA
Module/Function
Data transfer controller
(DTCa)
I/O ports
General I/O ports
Event link controller (ELC)
Multi-function pin controller (MPC)
Timers
Multi-function timer pulse
unit 2 (MTU2a)
Port output enable 2
(POE2a)
Compare match timer
(CMT)
Independent watchdog
timer (IWDTa)
Realtime clock (RTCA)
Low power timer (LPT)
8-bit timer (TMR)
Communication
functions
Serial communications
interfaces (SCIe, SCIf)
IrDA interface (IRDA)
I²C bus interface (RIIC)
Description
 Transfer modes: Normal transfer, repeat transfer, and block transfer
 Activation sources: Interrupts
 Chain transfer function
100-pin /64-pin
 I/O: 82/46
 Input: 2/2
 Pull-up resistors: 69/38
 Open-drain outputs: 61/34
 5-V tolerance: 4/4
 Event signals of 44 types can be directly connected to the module
 Operations of timer modules are selectable at event input
 Capable of event link operation for port B
Capable of selecting the input/output function from multiple pins
 (16 bits × 6 channels) × 1 unit
 Time bases for the six 16-bit timer channels can be provided via up to 16 pulse-input/output lines and
three pulse-input lines
 Select from among eight or seven counter-input clock signals for each channel (PCLK/1, PCLK/4,
PCLK/16, PCLK/64, PCLK/256, PCLK/1024, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than
channel 5, for which only four signals are available.
 Input capture function
 21 output compare/input capture registers
 Pulse output mode
 Complementary PWM output mode
 Reset synchronous PWM mode
 Phase-counting mode
 Capable of generating conversion start triggers for the A/D converter
Controls the high-impedance state of the MTU’s waveform output pins
 (16 bits × 2 channels) × 2 units
 Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
 14 bits × 1 channel
 Count clock: Dedicated low-speed on-chip oscillator for the IWDT
Frequency divided by 1, 16, 32, 64, 128, or 256
 Clock source: Sub-clock
 Calendar count mode or binary count mode selectable
 Interrupts: Alarm interrupt, periodic interrupt, and carry interrupt
 16 bits × 1 channel
 Clock source: Sub-clock, Dedicated low-speed on-chip oscillator for the IWDT
Frequency divided by 2, 4, 8, 16, or 32
 (8 bits × 2 channels) × 2 units
 Seven internal clocks (PCLK/1, PCLK/2, PCLK/8, PCLK/32, PCLK/64, PCLK/1024, and PCLK/8192)
and an external clock can be selected
 Pulse output and PWM output with any duty cycle are available
 Two channels can be cascaded and used as a 16-bit timer
 8 channels (channel 0, 1, 2, 5, 6, 8, and 9: SCIe, channel 12: SCIf)
 Serial communications modes: Asynchronous, clock synchronous, and smart card interface
 On-chip baud rate generator allows selection of the desired bit rate
 Choice of LSB-first or MSB-first transfer
 Average transfer rate clock can be input from MTU2 timers
 Simple I²C
 Simple SPI
 Master/slave mode supported (SCIf only)
 Start frame and information frame are included (SCIf only)
 Start-bit detection in asynchronous mode: Low level or falling edge is selectable
 1 channel (SCI5 used)
 Supports encoding/decoding of waveforms conforming to IrDA standard 1.0
 1 channel
 Communications formats:
I²C bus format/SMBus format
 Master mode or slave mode selectable
 Supports fast mode
R01DS0216EJ0110 Rev.1.10
Mar 31, 2016
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