RX113_16 Datasheet, PDF (86/131 Pages) Renesas Technology Corp – 32 MHz, 32-bit RX MCUs, 50 DMIPS, up to 512 Kbytes of flash memory

RX113 Group
5. Electrical Characteristics
Table 5.32 Timing of On-Chip Peripheral Modules (3)
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V,
T_a = –40 to +105°C, C = 30 pF
Item
Symbol
Min.
Max.
Unit*¹
Simple SCK clock cycle output (master)
SPI
SCK clock cycle input (slave)
t_SPcyc
4
65536
t_Pcyc
6
65536
t_Pcyc
SCK clock high pulse width
t_SPCKWH
0.4
0.6
t_SPcyc
SCK clock low pulse width
t_SPCKWL
0.4
0.6
t_SPcyc
SCK clock rise/fall time
t_SPCKr, t_SPCKf
—
20
ns
Data input setup time (master) 2.7 V or above
t_SU
65
—
ns
1.8 V or above
95
—
Data input setup time (slave)
40
—
Data input hold time
SS input setup time
SS input hold time
Data output delay time (master)
Data output delay time (slave)
2.7 V or above
t_H
t_LEAD
t_LAG
t_OD
40
—
ns
3
—
t_SPcyc
3
—
t_SPcyc
—
40
ns
—
65
1.8 V or above
—
100
Data output hold time (master) 2.7 V or above
t_OH
–10
—
ns
1.8 V or above
–20
—
Data output hold time (slave)
–10
—
Data rise/fall time
SS input rise/fall time
Slave access time
Slave output release time
t_Dr, t_Df
—
t_SSLr, t_SSLf
—
t_SA
—
t_REL
—
20
ns
20
ns
6
t_Pcyc
6
t_Pcyc
Note 1. t_Pcyc: PCLK cycle
Test
Conditions
Figure 5.42
Figure 5.43,
Figure 5.45
Figure 5.47,
Figure 5.48
R01DS0216EJ0110 Rev.1.10
Mar 31, 2016
Page 86 of 131