RX113_16 Datasheet, PDF(58/131 Page) Renesas Technology Corp – 32 MHz, 32-bit RX MCUs, 50 DMIPS, up to 512 Kbytes of flash memory

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RX113_16 Datasheet, PDF (58/131 Pages) Renesas Technology Corp – 32 MHz, 32-bit RX MCUs, 50 DMIPS, up to 512 Kbytes of flash memory

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RX113 Group

5. Electrical Characteristics

Table 5.7 DC Characteristics (5) (2/2)

Conditions: 1.8 V â¤ VCC = VCC_USB â¤ 3.6 V, 1.8 V â¤ AVCC0 â¤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = â40 to +105Â°C

Item

Symbol

Typ

Max

Unit

Test

Conditions

Supply Low-speed

current*1 operating

Normal

operating

No peripheral

operation*8

ICLK = 32.768 kHz ICC

4.3 â Î¼A

mode

All peripheral operation: ICLK = 32.768 kHz

15.0 â

Normal*9, *10

All peripheral operation: ICLK = 32.768kHz

Max.*9, *10

â 62

Sleep mode No peripheral

operation*8

ICLK = 32.768 kHz

2.3 â

All peripheral operation: ICLK = 32.768 kHz

Normal*9

8.6 â

Deep sleep No peripheral

mode

operation*8

ICLK = 32.768 kHz

1.7 â

All peripheral operation: ICLK = 32.768 kHz

Normal*9

7.0 â

Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up

MOSs are in the off state.

Note 2. Clock supply to the peripheral functions is stopped. This does not include BGO operation. The clock source is PLL. FCLK and

PCLK are set to divided by 64.

Note 3. Clocks are supplied to the peripheral functions. This does not include BGO operation. The clock source is PLL. FCLK and PCLK

are set to the same frequency as ICLK.

Note 4. Values when VCC = 3.3 V.

Note 5. This is the increase for programming or erasure of the ROM or E2 DataFlash during program execution.

Note 6. Clock supply to the peripheral functions is stopped. The clock source is PLL when ICLK = 12 MHz, and HOCO otherwise. FCLK

and PCLK are set to divided by 64.

Note 7. Clocks are supplied to the peripheral functions. The clock source is PLL when ICLK = 12 MHz, and HOCO otherwise. FCLK and

PCLK are set to the same frequency as ICLK.

Note 8. Clock supply to the peripheral functions is stopped. The clock source is the sub-clock oscillator. FCLK and PCLK are set to

divided by 64.

Note 9. Clocks are supplied to the peripheral functions. The clock source is the sub-clock oscillator. FCLK and PCLK are set to the

same frequency as ICLK.

Note 10. Values when the MSTPCRA.MSTPA17 bit (12-bit A/D converter module stop bit) is set to âtransition to the module stop state is

madeâ.

R01DS0216EJ0110 Rev.1.10

Mar 31, 2016

Page 58 of 131

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