RX113_16 Datasheet, PDF (115/131 Pages) Renesas Technology Corp – 32 MHz, 32-bit RX MCUs, 50 DMIPS, up to 512 Kbytes of flash memory

RX113 Group
5. Electrical Characteristics
5.11 Power-On Reset Circuit and Voltage Detection Circuit Characteristics
Table 5.57 Power-On Reset Circuit and Voltage Detection Circuit Characteristics (1)
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, T_a = –40 to +105°C
Item
Symbol Min. Typ. Max. Unit
Test Conditions
Voltage detection level
Power-on reset (POR)
Voltage detection circuit
(LVD1)*¹
V_POR
V_{det1_4}
V_{det1_5}
V_{det1_6}
V_{det1_7}
V_{det1_8}
V_{det1_9}
V_{det1_A}
V_{det1_B}
V_{det1_C}
V_{det1_D}
1.35
3.00
2.91
2.81
2.70
2.60
2.50
2.40
1.99
1.90
1.80
1.50
3.10
3.00
2.90
2.79
2.68
2.58
2.48
2.06
1.96
1.86
1.65
3.20
3.09
2.99
2.88
2.76
2.66
2.56
2.13
2.02
1.92
V Figure 5.62, Figure 5.63
V Figure 5.64
At falling edge VCC
Note: These characteristics apply when noise is not superimposed on the power supply. When a setting is made so that the voltage
detection level overlaps with that of the voltage detection circuit (LVD2), it cannot be specified which of LVD1 and LVD2 is used
for voltage detection.
Note 1. n in the symbol Vdet1_n denotes the value of the LVDLVLR.LVD1LVL[3:0] bits.
Table 5.58 Power-On Reset Circuit and Voltage Detection Circuit Characteristics (2)
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, T_a = –40 to +105°C
Item
Symbol Min. Typ. Max. Unit
Test Conditions
Voltage detection
level
Wait time after
power-on reset
cancellation
Voltage detection circuit
(LVD2)*¹
At normal startup*³
During fast startup time*⁴
V_{det2_0} 2.71 2.90 3.09 V Figure 5.65
V_{det2_1} 2.43 2.60 2.77
At falling edge VCC
V_{det2_2} 1.87 2.00 2.13
V_{det2_3}*² 1.69 1.80 1.91
t_POR
― 9.1 ― ms Figure 5.63
t_POR
― 1.6 ―
Wait time after voltage
monitoring 1 reset
cancellation
Power-on voltage monitoring
1 reset disabled*³
Power-on voltage monitoring
1 reset enabled*⁴
t_LVD1
― 568 ― μs Figure 5.64
― 100 ―
Wait time after voltage monitoring 2 reset cancellation t_LVD2
― 100 ― μs Figure 5.65
Response delay time
t_det
― ― 350 μs Figure 5.62
Minimum VCC down time*⁵
t_VOFF 350 ― ― μs Figure 5.62, VCC = 1.0 V or above
Power-on reset enable time
t_{W (POR)} 1
― ― ms Figure 5.63, VCC = below 1.0 V
LVD operation stabilization time (after LVD is enabled) Td _(E-A) ― ― 300 μs Figure 5.64, Figure 5.65
Hysteresis width (LVD1 and LVD2)
V_LVH
― 70 ― mV Vdet1_4 selected
― 60 ―
Vdet1_5 to 9, LVD2 selected
― 50 ―
When selection is from among Vdet1_A to B.
― 40 ―
When selection is from among Vdet1_C to D.
Note: These characteristics apply when noise is not superimposed on the power supply. When a setting is made so that the voltage
detection level overlaps with that of the voltage detection circuit (LVD1), it cannot be specified which of LVD1 and LVD2 is used
for voltage detection.
Note 1. n in the symbol Vdet2_n denotes the value of the LVDLVLR.LVD2LVL[3:0] bits.
Note 2. Vdet2_3 selection can be used only when the CMPA2 pin input voltage is selected and cannot be used when the power supply
voltage (VCC) is selected.
Note 3. When OFS1.(STUPLVD1REN, FASTSTUP) = 11b.
Note 4. When OFS1.(STUPLVD1REN, FASTSTUP) ≠ 11b.
Note 5. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels V_POR, V_det0,
V_det1, and V_det2 for the POR/LVD.
R01DS0216EJ0110 Rev.1.10
Mar 31, 2016
Page 115 of 131