E202075_HD404889 Datasheet, PDF (48/202 Pages) Renesas Technology Corp – Low-Voltage AS Microcomputers with On-Chip LCD Circuit

HD404889/HD404899/HD404878/HD404868 Series
External interrupt request flags (IF0, IF1: $001):
IF0 is set by a falling edge in the INT₀ input, and IF1 is set by a rising edge, falling edge, or both edges in
the INT₁ input (table 5).
Interrupt edge selection is performed by means of the edge detection select register (ESR: $006) (figure
12).
Table 5 External Interrupt Request Flags (IF0, IF1: $001)
External Interrupt Request Flags
(IF0, IF1)
0
1
Interrupt Request
No external interrupt request
External interrupt request generated
External interrupt masks (IM0, IM1: $001):
These bits mask interrupt requests by the external interrupt request flags (table 6).
Table 6 External Interrupt Mask (IM: $001)
External Interrupt Masks
(IM0, IM1)
0
1
Interrupt Request
External interrupt request enabled
External interrupt request masked (held pending)
Timer A interrupt request flag (IFTA: $002,0):
The timer A interrupt request flag is set by timer A overflow output (table 7).
Table 7 Timer A Interrupt Request Flag (IFTA: $002,0)
Timer A Interrupt Request
Flag(IFTA)
0
1
Interrupt Request
No timer A interrupt request
Timer A interrupt request generated
Timer A interrupt mask (IMTA: $002,1):
This bit masks an interrupt request by the timer A interrupt request flag (table 8).
Table 8 Timer A Interrupt Mask (IMTA: $002,1)
Timer A Interrupt Mask (IMTA)
0
1
Interrupt Request
Timer A interrupt request enabled
Timer A interrupt request masked (held pending)
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