E202075_HD404889 Datasheet, PDF (188/202 Pages) Renesas Technology Corp – Low-Voltage AS Microcomputers with On-Chip LCD Circuit

HD404889/HD404899/HD404878/HD404868 Series
Notes: 1. When the subsystem oscillator (32.768 kHz crystal oscillation) is used, use within the range
0.4 MHz≤f_OSC≤1.0 MHz or 1.6 MHz≤f_OSC≤4.5 MHz. The SSR1 bit of the system clock select
register (SSR) should be set to 0 and 1, respectively.
2. The oscillation settling time is defined as follows:
(1) The time required for the oscillation to settle after V_CC has reached min. at power-on.
(2) The time required for the oscillation to settle after RESET input has gone low when stop
mode is cleared.
To ensure enough time for the oscillation to settle at power-on hold the RESET input low for at
least time t_RC. The oscillation settling time will depend on the circuit constants and stray
capacitance. The resonator should be determined in consultation with the resonator
manufacturer. With regard to the system clock (OSC₁, OSC₂), bits MIS1 and MIS0 in the
miscellaneous register (MIS) should be set according to the oscillation settling time of the
resonator used.
3. See figure 104.
4. See figure 105.
5. See figure 106.
Serial Interface Timing Characteristics (HD404888, HD4048812, HD404889, HD404898, HD4048912,
HD404899, HD404874, HD404878, HD404864, HD404868: V_CC=1.8V to 5.5V, GND=0V, T_a=–20°C to
+75°C;, HCD404889, HCD404899, HCD404878: V_CC =1.8V to 5.5V, GND=0V, Ta=+75°C;
HD4074889, HD4074899, HD4074869: V_CC=2.0V to 5.5V, GND=0V, T_a=–20°C to +75°C, unless
otherwise specified)
Item
Symbol
Serial clock cycle time t_Scyc
Serial clock high-level t_SCKH
width
Serial clock low-level t_SCKL
width
Serial clock rise time
Serial clock fall time
Serial output data
delay time
t_{SC Kr}
t_SCKf
t_DSO
Serial input data setup t_SSI
time
Serial input data hold t_HSI
time
Pins
SCK
SCK
SCK
SCK
SCK
SO
SI
SI
min.
1
0.4
0.4
—
—
—
200
200
typ. max.
——
——
——
— 100
— 100
— 300
——
——
Unit
t_cyc
t_Scyc
Test conditions
Notes
See load in figure 108 1
See load in figure 108 1
t_Scyc See load in figure 108 1
ns See load in figure 108 1
ns See load in figure 108 1
ns See load in figure 108 1
ns
1
ns
1
186