E202075_HD404889 Datasheet, PDF (32/202 Pages) Renesas Technology Corp – Low-Voltage AS Microcomputers with On-Chip LCD Circuit

HD404889/HD404899/HD404878/HD404868 Series
Bits in the interrupt control bit area and register flag area can be set and reset by the SEM or SEMD
instruction and the REM or REMD instruction, and tested by the TM or TMD instruction. They are not
affected by any other instructions.
The following restrictions apply to individual bits.
IE
IM
LSON
IF
ICSF
ICEF
GEF
RSP
WDON
ADSF^*
DTON
Not Used
SEM/SEMD
Allowed
Not executed
Allowed
Not executed
Allowed
Allowed
Not executed in active mode
Used in subactive mode
Not executed
REM/REMD
Allowed
Allowed
Allowed
Allowed
Not executed
Inhibited
Allowed
Not executed
TM/TMD
Allowed
Allowed
Inhibited
Inhibited
Inhibited
Allowed
Allowed
Inhibited
Notes : _{The WDON bit is reset only by stop mode clearance by means of an MCU reset.}
Do not use the REM or REMD instruction on the ADSF bit during A/D conversion.
The DTON bit is always in the reset state in active mode.
If the TM or TMD instruction is used on a bit for which its use is prohibited, or on a nonexistent
bit, the status flag value will be undetermined.
* Applies to HD404889, HD404899, and HD404868 Series.
Figure 4 Instruction Restrictions
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