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E202075_HD404889 Datasheet, PDF (175/202 Pages) Renesas Technology Corp – Low-Voltage AS Microcomputers with On-Chip LCD Circuit
HD404889/HD404899/HD404878/HD404868 Series
Table 38 ROM Address Instructions
Operation
Mnemonic Operation Code
Branch on status 1
BR b
Long branch on status 1 BRL u
Long jump
unconditionally
Subroutine jump on
status 1
JMPL u
CAL a
1 1 b7 b6 b5 b4 b3 b2 b1 b0
0 1 0 1 1 1 p3 p2 p1 p0
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
0 1 0 1 0 1 p3 p2 p1 p0
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
0 1 1 1 a5 a4 a3 a2 a1 a0
Long subroutine jump
on status 1
Table branch
Return from subroutine
CALL u
TBR p
RTN
0 1 0 1 1 0 p3 p2 p1 p0
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
0 0 1 0 1 1 p3 p2 p1 p0
0 0 0 0 0 10 0 0 0
Return from interrupt
RTNI
0 0 0 0 0 10 0 0 1
Function
1 → IE,
carry restored
Words/
Status Cycles
1
1/1
1
2/2
2/2
1
1/2
1
2/2
1
1/1
1/3
ST
1/1
Table 39 Input/Output Instructions
Operation
Set discrete I/O latch
Set discrete I/O latch
direct
Reset discrete I/O latch
Reset discrete I/O latch
direct
Test discrete I/O latch
Test discrete I/O latch
direct
Load A from R-port
register
Load B from R-port
register
Load R-port register
from A
Load R-port register
from B
Pattern generation
Mnemonic Operation Code
SED
0 0 1 1 1 00 1 0 0
SEDD m
1 0 1 1 1 0 m3 m2 m1 m0
Function
1 → D (Y)
1 → D (m)
RED
REDD m
0 0 0 1 1 00 1 0 0
1 0 0 1 1 0 m3 m2 m1 m0
0 → D (Y)
0 → D (m)
TD
TDD m
0 0 1 1 1 00 0 0 0
1 0 1 0 1 0 m3 m2 m1 m0
LAR m
1 0 0 1 0 1 m3 m2 m1 m0 R (m) → A
LBR m
1 0 0 1 0 0 m3 m2 m1 m0 R (m) → B
LRA m
1 0 1 1 0 1 m3 m2 m1 m0 A → R (m)
LRB m
1 0 1 1 0 0 m3 m2 m1 m0 B → R (m)
Pp
0 1 1 0 1 1 p3 p2 p1 p0
Words/
Status Cycles
1/1
1/1
1/1
1/1
D (Y) 1/1
D (m) 1/1
1/1
1/1
1/1
1/1
1/2
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