E202075_HD404889 Datasheet, PDF (124/202 Pages) Renesas Technology Corp – Low-Voltage AS Microcomputers with On-Chip LCD Circuit

HD404889/HD404899/HD404878/HD404868 Series
Bit 1 (SMR21) of serial mode register 2 (SMR2) performs SO pin high/low control in the idle state. The
SO pin changes at the same time as the high/low write.
Serial mode register 2 (SMR2: $025)
Bit
Read/Write
Initial value on reset
Bit name
3
2
1
0
—
W
W
—
—
0 undeternined —
— SMR22 SMR21
SMR21 Idle high/low control
0 SO pin set to low-level output in idle state
1 _{SO pin set to high-level output in idle state}
SMR22
0
1
R22/SI/SO pin output buffer control
PMOS active
PMOS off (NMOS open-drain output)
Figure 67 Serial Mode Register 2 (SMR2)
Serial data register (SRL: $026, SRU: $027):
The serial data register (SRL, SRU) has the following functions. See figures 68 and 69.
• Transmit data write and shift operations
• Receive data shift and read operations
The data written to the serial data register (SRL, SRU) is output LSB-first from the SO pin in
synchronization with the falling edge of the serial clock.
External data input LSB-first from the SI pin is latched in synchronization with the rising edge of the serial
clock. Figure 70 shows the serial clock and data input/output timing chart.
Writing and reading of the serial data register (SRL, SRU) must be performed only after data
transmission/reception is completed. The data contents are not guaranteed if a read or write is performed
during data transmission or reception.
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