E202075_HD404889 Datasheet, PDF (120/202 Pages) Renesas Technology Corp – Low-Voltage AS Microcomputers with On-Chip LCD Circuit

HD404889/HD404899/HD404878/HD404868 Series
Serial clock error detection (external clock mode):
The serial interface will operate incorrectly in the transfer state if external noise results in unnecessary
pulses being added to the serial clock. Serial clock error detection in such cases is carried out as shown in
figure 65.
If more than eight serial clock pulses are input due to external noise while in the transfer state, at the eighth
clock pulse (including any external noise pulses), the octal counter is cleared to 000 and the serial interrupt
request flag (IFS) is set. At the same time, the serial interface exits the transfer state and enters the serial
clock wait state, but returns to the transfer state at the next regular clock pulse falling edge.
Meanwhile, in the interrupt handling routine, transfer end processing is performed, the serial interrupt
request flag is reset, and a dummy write is performed into serial mode register 1 (SMR1). The serial
interface then returns to the STS wait state, and the serial interrupt request flag (IFS) is set again. It is
therefore possible to detect a serial clock error by testing the serial interrupt request flag after the dummy
write to serial mode register 1.
Usage notes:
• Initialization after register modification
If a port mode register 3 (PMR3) write is performed in the serial clock wait state or transfer state, a
serial mode register 1 (SMR1) write should be performed again to initialize the serial interface.
• Serial interrupt request flag (IFS:$023, 2) setting
If a serial mode register 1 (SMR1) write or STS instruction is executed during the first low-level
interval of the serial clock in the transfer state, the serial interrupt request flag (IFS) will not be set. To
ensure that the serial interrupt request flag (IFS) is properly set in this case, programming is required to
make sure that the SCK pin is in the 1 state (by executing an input instruction for the R2 port) before
executing a serial mode register 1 (SMR1) write or an STS instruction.
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