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E202075_HD404889 Datasheet, PDF (29/202 Pages) Renesas Technology Corp – Low-Voltage AS Microcomputers with On-Chip LCD Circuit
HD404889/HD404899/HD404878/HD404868 Series
HD404868 Series
$000
RAM-mapped
register area
$03F
$040 Memory register (MR) area
$04F
(16 digits)
$050
LCD data area
(24 digits)
$067
$068
$08F
$090
Not used
Data
(304 digits)
$1BF
$1C0
Not used
$3BF
$3C0
$3FF
Stack area
(64 digits)
$000
$001
$002
Interrupt control bit area
$003
$004 Speed Select Reg.
(SSR) W
$005 Miscellaneous Reg.
(MIS) W
$006 Edge Select Reg.
(ESR) W
$007
Not used
$008 Port Mode Reg.0
(PMR0) W
$009 Port Mode Reg.1
(PMR1) W
$00A Port Mode Reg.2
(PMR2) W
$00B Port Mode Reg.3
(PMR3) W
$00C Port Mode Reg.4
(PMR4) W
$00D Module Standby Reg.1
(MSR1) W
$00E Module Standby Reg.2
(MSR2) W
$00F Timer Mode Reg.A
(TMA) W
$010 Timer Mode Reg.B1
(TMB1) W
$011 Timer Mode Reg.B2
(TMB2) W
$012 Timer B
(TRBL/TWBL) R/W
*
$013
(TRBU/TWBU) R/W
$014 Timer Mode Reg.C1
(TMC1) W
$015 Timer Mode Reg.C2
(TMC2) W
$016 Timer C
(TRCL/TWCL) R/W
$017
(TRCU/TWCU) R/W
$018
$019
$01A
$01B
$01C
Not used
$01D
$01E
$01F
$020
$021
$022
Register flag area
$023
$024 Serial Mode Reg.1
(SMR1) W
$025 Serial Mode Reg.2
(SMR2) W
$026 Serial Mode Reg.Lower
(SRL) R/W
$027 Serial Mode Reg.Upper
(SRU) R/W
$028 A/D Mode reg.
(AMR) W
$029 A/D Data Reg.Lower
(ADRL) R
$02A A/D Data Reg.Middle
(ADRM) R
$02B A/D Data Reg.Upper
(ADRU) R
$02C LCD Control Reg.
(LCR) W
$02D LCD Mode Reg.
(LMR) W
$02E Buzzer Mode Reg.
(BMR) W
$02F
Not used
$030
$031
$032
$033
Port D0–D3 DCR
Port D4–D7 DCR
Port D8–D9 DCR
Not used
(DCD0) W
(DCD1) W
(DCD2) W
$034 Port R0 DCR
(DCR0) W
$035 Port R1 DCR
(DCR1) W
$036 Port R2 DCR
(DCR2) W
$037 Port R3 DCR
(DCR3) W
$038 Port R4 DCR
(DCR4) W
$039 Port R5 DCR
(DCR5) W
$03A Port R6 DCR
(DCR6) W
$03B Port R7 DCR
(DCR7) W
$03C
$03D
$03E
Not used
$03F
Notes:
R : Read
W : Write
R/W: Read/Write
*Two registers are mapped
onto the same address
($012, $013, $016, $017).
$012 Timer Read Reg.B Lower
$013 Timer Read Reg.B Upper
(TRBL) R Timer Write Reg.B Lower
(TRBU) R Timer Write Reg.B Upper
(TWBL) W
(TWBU) W
$016 Timer Read Reg.C Lower
$017 Timer Read Reg.C Upper
(TRCL) R Timer Write Reg.C Lower
(TRCU) R Timer Write Reg.C Upper
(TWCL) W
(TWCU) W
Figure 2 RAM Memory Map (cont)
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