E202075_HD404889 Datasheet, PDF (45/202 Pages) Renesas Technology Corp – Low-Voltage AS Microcomputers with On-Chip LCD Circuit

HD404889/HD404899/HD404878/HD404868 Series
Table 3 Interrupt Processing and Activation Conditions
Interrupt Source
WU₀ to
Interrupt Control Bit WU₃
INT₀
INT₁
Timer B or
Timer A Timer D Timer C
IE
1
1
1
1
1
1
IFWU·IMWU
1
0
0
0
0
0
IF0·IM0
*
1
0
0
0
0
IF1·IM1
*
*
1
0
0
0
IFTA·IMTA
*
*
*
1
0
0
IFTB·IMTB+IFTD·IMTD *
*
*
*
1
0
IFTC·IMTC
*
*
*
*
*
1
IFAD·IMAD+IFS·IMS *
*
*
*
*
*
Note: * Operation is not affected whether the value is 0 or 1.
A/D or
Serial
1
0
0
0
0
0
0
1
Instruction cycle
1
2
3
4
5
6
Instruction
execution*
Interrupt
acceptance
Save to stack
IE reset
Save to stack
Vector address
generated
Execution of JMPL instruction
at vector address
Execution of
instruction at
start address of
interrupt routine
Note: The stack is accessed and the IE reset after the instruction is executed, even if it is a 2cycle instruction.
Figure 10 Interrupt Sequence
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