E202075_HD404889 Datasheet, PDF (107/202 Pages) Renesas Technology Corp – Low-Voltage AS Microcomputers with On-Chip LCD Circuit

HD404889/HD404899/HD404878/HD404868 Series
Timer D Operation
• Free-running/reload timer:
Free-running/reload timer operation, the input clock source, and the prescaler division ratio are selected
by means of timer mode register D1 (TMD1).
Timer D is initialized to the value written to timer write register D (TWDL, TWDU) by software, and
counts up by 1 each time the input clock is input. When the input clock is input after the timer D value
reaches $FF, overflow output is generated. Timer D is then set to the value in timer write register D
(TWDL, TWDU) if the reload timer function is selected, or to $00 if the free-running timer function is
selected, and starts counting up again.
Overflow output sets the timer D interrupt request flag (IFTD). This flag is reset by the program or by
an MCU reset. For details, see figure 3, Interrupt Control Bit and Register Flag Area Configuration,
and table 1, Initial Values after MCU Reset.
• External event counter operation:
When external event input is designated for the input clock, timer D operates as an external event
counter. When external event input is used, the R1₁/EVND pin is designated as the EVND pin by port
mode register 2 (PMR2).
The external event detected edge for timer D can be designated as a falling edge, rising edge, or both
falling and rising edges in the input signal by means of timer mode register D2 (TMD2). If both falling
and rising edges are selected, the input signal falling and rising edge interval should be at least 2tcyc.
Timer D counts up by 1 each time the edge selected by timer mode register D2 (TMD2) is detected.
Other operations are the same as for the free-running/reload timer function.
• Input capture timer operation:
The input capture timer function is used to measure the time between trigger input edges input at the
EVND pin.
The trigger input edge can be designated as a falling edge, rising edge, or both falling and rising edges
by means of timer mode register D2 (TMD2).
When a trigger input edge is detected at the EVND pin, the current timer D value is stored in timer read
register D (TRDL, TRDU), and the timer D interrupt request flag (IFTD) and input capture status flag
(ICSF) are set. At the same time, timer D is reset to $00 and continues counting up.
If the next trigger input edge is input while the input capture status flag (ICSF) is set, or if timer D
overflows, the input capture error flag (ICEF) is set.
The input capture status flag (ICSF) and input capture error flag (ICEF) are reset to 0 by an MCU reset
or by writing 0 to them.
When timer D is set to operate as an input capture timer, it is reset to $00.
105