E202075_HD404889 Datasheet, PDF (42/202 Pages) Renesas Technology Corp – Low-Voltage AS Microcomputers with On-Chip LCD Circuit

HD404889/HD404899/HD404878/HD404868 Series
Table 1 (2) Initial Values after MCU Reset
Item
Abbr.
Carry flag
(CA)
Accumulator (A)
B register
(B)
W register
(W)
X/SPX register (X/SPX)
Y/SPY register (Y/SPY)
RAM
After Stop Mode Clearance by WU₀ to
WU₃ Input
Retain value immediately prior to
entering stop mode
After Other MCU Reset
Value immediately prior to MCU reset is not
guaranteed. Must be initialized by program.
Interrupts
There are a total of nine interrupt sources, comprising wakeup input (WU₀ to WU₃), external interrupts
(INT₀, INT₁), timer/counter (timer A, timer B, timer C, timer D) interrupts, a serial interface interrupt, and
an A/D converter interrupt.
Each interrupt source is provided with an interrupt request flag, interrupt mask, and vector address, used for
storing and controlling interrupt requests. In addition, an interrupt enable flag is provided to control
interrupts as a whole.
Of the interrupt sources, timers B and D share the same vector address, and the A/D converter and serial
interface also share the same vector address. Software must therefore determine which of the interrupt
sources is requesting an interrupt at the start of interrupt handling.
Interrupt control bits and interrupt handling:
The interrupt control bits are mapped onto RAM addresses $000 to $003 and $022 to $023, and can be
accessed by RAM bit manipulation instructions. However, the interrupt request flags (IF) cannot be set by
software. When the MCU is reset, the interrupt enable flag (IE) and interrupt request flags (IF) are
initialized to 0, and the interrupt masks (IM) are initialized to 1.
Figure 9 shows a block diagram of the interrupt control circuit, table 2 shows interrupt priorities and vector
addresses, and table 3 lists the conditions for executing interrupt handling for each of the nine kinds of
interrupt source. When the interrupt request flag is set to 1 and the interrupt mask is cleared to 0, an
interrupt is requested. If the interrupt enable flag is set to 1 at this time, interrupt handling is started. The
vector address corresponding to the interrupt source is generated by the priority control circuit.
The interrupt handling sequence is shown in figure 10, and the interrupt handling flowchart in figure 11.
When an interrupt is accepted, execution of the previous instruction is completed in the first cycle. In the
second cycle, the interrupt enable flag (IE) is reset. In the second and third cycles, the contents of the carry
flag, status flag, and program counter are saved on the stack. In the third cycle, a jump is made to the
vector address and instruction execution is resumed from that address.
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