MC92314 Datasheet, PDF (76/100 Pages) Motorola, Inc – DVB-T Single Chip Demodulator Application Note

Freescale Semiconductor, Inc.
DVB-T Demodulator Interfaces
polarity should be chosen and fed to a RC lowpass filter to obtain the control voltage to be fed
into the tuner. Refer to Section 5 for the appropriate circuit values.
Common to the VCXO and the AGC control are the following output characteristics:
• Signal level: The voltage level delivered by the device is within the range [0.3 V above
V_SS .. 0.3 V below V_DD], leading to the range between 0.3 V and 3 V for the nominal supply
voltage of 3.3 V.
• Maximum current provided: 4 mA
4.3.4.1 VCXO Control Loop
The differential control lines for the VCXO control are pin 41 (CLKCTLP) and pin 46 (CLKCTLN).
The input at the tuner must meet the following characteristics:
n _{• VCXO Pulling range: minimum +/-2 KHz, maximum +/-6 KHz. This number applies to the}
tio ^{clock signal, not to the clock/2 signal. This range must be maintained after taking into}
a ^{account all possible deviations, e.g. tolerance, temperature drift and ageing.}
• VCXO Quiescent Frequency: to keep the lock time as short as possible the deviation of
rm the VCXO frequency corresponding to the center value of the CLKCTL output voltage
fo ^{should be as close as possible to the nominal frequency of (256 / 7) MHz. For best results}
is is recommended not to exceed +/-10 ppm, this ensures fast response of the time
In synchronisation circuitry.
y • Direction: The direction of pulling the OFDM device assumes can be set using Bit O[16] of
r _{OFDM register 2. Default value is decreasing voltage -> increasing frequency.}
ina _{4.3.4.2 AGC Control Loop}
lim ^{The differential control lines for the AGC amplifier control are pin 36 (AGCCTLP) and pin 40}
(AGCCTLN). The input at the tuner must meet the following characteristics:
Pre • AGC Range: 76 dB minimum for the worst case signal levels (this is dependent upon the
sensitivity and the desired range).
• Direction: The direction of pulling the OFDM block assumes can be set using Bit O[21] of
OFDM register 2. Default value is decreasing voltage -> increasing gain.
4.4 MPEG-2 Output Interface of the MC92314
The interface to the MPEG-2 demultiplexer or CA processor after the DVB-T frontend consists
of the following lines:
• MPEG-2 Byte clock: The TRCLOCK output (pin 120) maintains the overall clock of the
MPEG-2 transport stream. Its average frequency corresponds to the datarate available for
the transmitted DVB-T signal.
MOTOROLA
4-28
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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