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| MC92314 Datasheet, PDF (58/100 Pages) Motorola, Inc – DVB-T Single Chip Demodulator Application Note | |||
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Freescale Semiconductor, Inc.
DVB-T Demodulator Interfaces
4 bits (s68 to s71) contain status information concerning the decoding process. The TPS registers
are updated continuously as the TPS data are decoded from the pilot information.
To achieve read access to the TPS data this update process must be suspended prior to reading.
This is accomplished by a write access to the TPS index register. Following this write the desired
TPS data can be read.
Table 4-2. TPS signalling information and format (see reference [1-1])
Bit number
Values
Purpose/Content
s0
s1 - s16
0011010111101110
or
1100101000010001
Initialization bit for 2-DPSK modulation of TPS
Synchronisation word for 1st and 3rd TPS block
Synchronisation word for 2nd and 4th TPS block
s17 - s22
tion s23, s24
ma s25, s26
Infor s27, s28, s29
Preliminary s30, s31, s32
010111
00: Frame #1
01: Frame #2
10: Frame #3
11: Frame #4
00: QPSK
01: 16-QAM
10: 64-QAM
11: reserved
000: Non hierarchical
001: α = 1
010: α = 2
011: α = 4
100: reserved
...
111: reserved
000: 1/2
001: 2/3
010: 3/4
011: 5/6
100: 7/8
101: reserved
...
111: reserved
Length indicator
Frame number within the superframe
Constellation
Hierarchy information (α-value)
Code rate, HP stream
s33, s34, s35
s36, s37
s38, s39
same as above
00: 1/32
01: 1/16
10: 1/8
11: 1/4
00: 2K mode
01: 8K mode
10: reserved
11: reserved
Code rate, LP stream
Guard interval
Transmission mode
s40 - s53
s54 - s67
s68
s69
s70
s71
all set to â0â
BCH code
TPS lock
TPS valid
Clock/Time Sync Lock
AFC Lock
Reserved for future use
Error protection
TPS acquired indicator
unaveraged TPS indicator
Timing Synchronisation achieved lock
AFC achieved lock
MOTOROLA
4-10
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
For More Information On This Product,
Go to: www.freescale.com
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