MC92314 Datasheet, PDF (62/100 Pages) Motorola, Inc – DVB-T Single Chip Demodulator Application Note

Freescale Semiconductor, Inc.
DVB-T Demodulator Interfaces
with ‘XXXX’ being the programmed value (4 bit 2’s compement numbers) and ‘C’ being a
constant.
For a description of the filter structure see paragraph 3.2.2.3.
4.2.2.1.6 AGC/AFC Integrator Gain ($0F, R/W)
This register allows control of the coefficients for the AGC and the AFC filter integrators. Bits [7:4]
control the gain of the AGC integrator, bits [3:0] control the gain of the AFC integrator. The values
programmed here increase or decrease the default values instead of setting the coefficients
directly, therefore the default value is $00.
4.2.2.1.7 AFC Sweep Start [1:0] ($11:$10, R/W)
This registers holds the initial value of the accumulator for the coarse AFC frequency sweep
algorithm. This corresponds to the start point of the sweep through the available range when the
n ^{sweep starts, e.g. after a soft reset. Once synchronisation has been achieved, it may be possible}
tio ^{to reduce the lock-in time of subsequent acquisition cycles by trying the previous lock-in value.}
a ^{4.2.2.1.8 AFC Threshold [1:0] ($13:$12, R/W)}
This register holds the threshold value to switch off coarse AFC as a 16-bit value (register 0 at
rm ^{address $12 corresponds to the LS byte, register 1 at address $13 to the MS byte). By adjusting}
fo ^{this value, it is possible to optimise the AFC acquisition time.}
In ^{4.2.2.1.9 AGC Threshold ($14, R/W)}
This register holds the compare value for the AGC module. By changing this value it is possible
ry ^{to alter the input peak-to-mean ratio of the OFDM time domain signal and therefore find the}
a ^{optimal compromise between quantisation noise and clipping.}
in _{4.2.2.1.10 AFC Sweep Speed [1:0] ($16:$15, R/W)}
lim ^{This registers contains the increment value of the AFC offset stepsize during the sweep.}
e 4.2.2.1.11 Channel State Estimation [3:0] ($1A:$17, R/W)
Pr ^{This registers controls the generation of soft-decision information out of the Channel State}
Estimation block. As the terrestrial reception is subject to several kinds of disturbance (see
Section 2) the optimal setting w.r.t. e.g. to noise is not optimal w.r.t. to single tone or co-channel
interference. The default values in this register are optimised for best noise performance. In
Section 5 another set of values for best CCI performance is given.
4.2.2.1.12 Internal Register ($21, W)
This register is used to select internal configurations of the OFDM. There’s no need to use it for
normal operation, but it can be used to enable the AGC Fix registers in the same way like the
VCXO Fix registers described above. Refer to paragraph 4.2.2.1.13 for the value necessary.
4.2.2.1.13 AGC Fix [1:0] ($26:$25, W)
This 2-byte register can be used to set the voltage at the σδ-output for the AGC circuit in the
tuner, mainly intended for test purposes, not for normal operation. To use them the value of $BA
must be written to the Internal register at address $21. Afterwards the AGC Fix register can be
MOTOROLA
4-14
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
For More Information On This Product,
Go to: www.freescale.com