MC92314 Datasheet, PDF (51/100 Pages) Motorola, Inc – DVB-T Single Chip Demodulator Application Note

Freescale Semiconductor, Inc.
DVB-T Demodulator Interfaces
4.2.1.2 Stop Condition
Whenever SDA goes from low to high while SCL is constant high a data transfer sequence is
finished.
SDA
SCL
“p”
4.2.1.3 Transmitting “1” and “0”
Whenever SDA changes its value SCL must be low.
tion ^SDA
a _SCL
“0”
“1”
form ^{4.2.1.4 Data Transfer Sequence}
In ^{Each I2C bus member has a 7-Bit address. The data transfer starts with the start condition and}
is followed by the 7-Bit address of the slave to be selected. The 8th bit after the address
y _{determines the direction of the initiated data transfer. The selected slave has to acknowledge the}
r _{successful receipt of its address. If the transfer should be a read transfer from slave to the}
a _{master, the slave starts transmitting byte by byte until the master forces the stop condition. Each}
in byte will be acknowledged by the master. A new transfer sequence can start immediately issuing
Prelim ^{a new start condition instead of the stop condition.}
S 7-Bit address 1 0
data byte 1
0
data byte 2
1P
start condition
read access
acknowledge from slave
: from master
acknowledge from master acknowledge from master
: from slave
stop condition
Figure 4-2. Read Sequence
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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4-3