MC92314 Datasheet, PDF (61/100 Pages) Motorola, Inc – DVB-T Single Chip Demodulator Application Note

Freescale Semiconductor, Inc.
DVB-T Demodulator Interfaces
Table 4-5. OFDM Register 2 ($0D, W)
FTSE BIT[7] AFCS BIT[6]
AGCS BIT[5]
0: FTS
DISABLED (I.V.)
0: INCR. FREQ.
0: INCR. VOLT ->
INCR. GAIN
1: FTS
ENABLED
1: DECR.
FREQ. (I.V.)
1: DECR. VOLT ->
INCR. GAIN (I.V.)
RESERVED
BIT[4:3]
10: (I.V.)
UHFI BIT[2]
0: UPPER S.B.
1: LOWER S.B.
(I.V.)
ADCM BIT[1]
CLKS BIT[0]
0: 2’S COMPLEMENT
(I.V.)
0: INCR. VOLT ->
INCR. FREQ.
1: OFFSET BINARY
1: DECR. VOLT ->
INCR. FREQ. (I.V.)
OFDM Clock VCXO Slope [CLKS]: The direction of the VCXO control signal to adjust the
OFDM system clock can be adjusted using this register (of course it is also possible to select the
appropriate control line, see the paragraph 4.3.4 Tuner Control signals from the MC92314).
n _{Initial value is that decreasing voltage from the OFDM block is assumed to result in increasing}
tio ^{frequency of the VCXO.}
a _{Tuner ADC Input Format [ADCM]: This register serves to adjust the input stage of the OFDM}
m block to the ADC in the tuner. The initial value is set to 2’s complement.
for ^{UHF Demodulation Sideband [UHFI]: Normally the LO in the tuner’s downconverter is located}
above the received channel. So the RF spectrum is inverted when arriving at the OFDM block.
In _{Using this register it is possible to select the appropriate sideband. The initial value is set}
y ^{corresponding to the inverted spectrum.}
ar AGC Slope [AGCS]: The direction of the AGC control signal to adjust the tuner’s AGC amplifier
in ^{can be adjusted using this register. The initial value is set that the OFDM block assumes}
increasing gain with decreasing voltage.
lim _{AFC Slope [AFCS]: This bit sets the direction of the AFC control signal to compensate for LO}
e _{drifts in the tuner. The initial value is set for the lower sideband used in the tuner.}
Pr _{Fine Time Sync Enable [FTSE]: This bit enables the Fine Time synchronisation loop to control}
the VCXO via the σδ-DAC in the device. To test the connection from the device to the tuner it is
possible to disable this connection and to write into the VCXO Fix register.
NOTE
Please refer to Section 5 for additional details on the initialisation of
the OFDM block.
4.2.2.1.5 Clock Loop Filter Coefficients ($0E, R/W)
This register sets the coefficients for the clock loop filter coefficients. Bits [7:4] control the gain of
the proportional part, bits [3:0] control the gain of the integrator. The coefficients actual used are
of the form
C + 1 * 2^XXXX
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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