MC92314 Datasheet, PDF (75/100 Pages) Motorola, Inc – DVB-T Single Chip Demodulator Application Note

Freescale Semiconductor, Inc.
DVB-T Demodulator Interfaces
clock
>=5ns >=5ns
>=5ns >=5ns
clock/2
>=5ns
tion _{ADC data}
ma Figure 4-6. Clock and Data phase relationship
for _{4.3.3 Input from the Tuner Analog-to-Digital Converter}
In _{The digital output of the ADC in the tuner must meet the following characteristics:}
ry ^{• Format: 8-bit TTL compatible, either 2’s complement or offset binary. The format can be set}
a ^{using bit O[17] in OFDM register 2. Default setting is 2’s complement. The 8 bits are fed into}
in ^{the ADCDATA[7:0] of the OFDM block.}
• Sampling frequency: 18.29 MHz = clock/2.
lim ^{• Clocking: See Figure 4-6. Clock frequency is clock/2. The samples are clocked into the}
e ^{OFDM block with the rising edge of the clock signal, using the clock/2 as enable signal.}
Pr ^{The rising edge of the 36.57 MHz clock is the active edge to clock the data into the OFDM}
block. Therefore the data signals should change during the falling edge of the clock/2 signal
to minimise the effects of skew, as given in Figure 4-6.
• Analog signal before the ADC: The centre frequency of the analog IF signal before the
ADC is positioned at an IF of 4.57 MHz.
The OFDM can compensate an offset in frequency, e.g. due to deviations of the local
oscillator in the tuner, of +/-50 KHz.
OFDM signal RMS: In the absence of noise or interference the peak to RMS ratio should be
14 dB. In an 8-bit ADC with digital level 128 (peak) this leads to a RMS digital level of 25.
4.3.4 Tuner Control signals from the MC92314
The VCXO in the tuner and the AGC amplifier are controlled by the OFDM block by differential
σδ-output lines (..P for positive and ..N for negative direction). The line giving the appropriate
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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