MC92314 Datasheet, PDF (74/100 Pages) Motorola, Inc – DVB-T Single Chip Demodulator Application Note

Freescale Semiconductor, Inc.
DVB-T Demodulator Interfaces
• Third order input intercept point:
>-10 dBm at maximum gain (i.e. when the noise figure meets the number stated above);
>+10 dBm if the frontend gain is reduced by 20 dB;,
>+15 dBm at 30 dB gain reduction.
• Image rejection: >53 dB.
• LO synthesiser step size: dependent from the offset of the OFDM center frequency w.r.t.
the centre frequency of the transmission channel.
• LO synthesiser phase noise:
>65 dBc between 200 Hz and 2 KHz offset;
>83 dBc at 10 KHz offset;
>130 dBc at offset frequencies above 1.4 MHz.
n _{The numbers are obtained using the total LO power relative to the SSB noise power in 1 Hz}
tio ^bandwidth.
a ^{• Frequency accuracy (measured at channel 69): +/-50 KHz maximum. All impairments of}
the LO’s (e.g. tolerance, temperature drift and ageing) for the conversion from UHF/VHF to
m _{1st IF and the conversion to the 2nd IF must be covered with this value.}
for ^{• 1st IF centre frequency: For the maximum step size (as stated above), an integer multiple}
of the RF LO synthesiser step size.
In _{• Final IF centre frequency (before ADC): 32/7 MHz for 8 MHz channel bandwidth}
y (7.61 MHz used BW); 4 MHz for 7 MHz channels (6.66 MHz used).
r _{• ADC output signal SNR: The ‘tuner-SNR’ must be >33 dB. It is obtained by comparing (at}
a _{the output of the ADC) the RMS of the OFDM signal (specified in the paragraph ‘4.3.3 Input}
in _{from the Tuner Analog-to-Digital Converter’) with all noise and distortion added by the tuner.}
lim ^{• Frequency response: The following frequency values are relative to the center of the}
OFDM signal spectrum, the frequency response values are valid for the overall tuner, i.e.
e _{from the RF input until the digital output.}
Pr ^{<3.8 MHz: deviation less than +/-3 dB}
4.35 MHz: rejection better than 15 dB
4.7 MHz: rejection better than 30 dB
>5.3 MHz: rejection better than 70 dB
4.3.2 Clock Signals
The overall DVB-T system clock of 256/7 ~ 36.57 MHz is provided by a VCXO in the tuner and
must be fed to pin 61 (CLK) of the OFDM device. It is labelled ‘clock’ in Figure 4-6. Division by 2
provides the ADC clock signal (‘clock/2’) that is expected at pin 33, CLKEN18.
The duty cycle for both signals must be between 40/60 and 60/40 with TTL compatible levels. As
the inputs of the OFDM device are 5 V compatible either 3.3 V or 5 V signals are possible.
MOTOROLA
4-26
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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