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MC92314 Datasheet, PDF (59/100 Pages) Motorola, Inc – DVB-T Single Chip Demodulator Application Note
Freescale Semiconductor, Inc.
DVB-T Demodulator Interfaces
NOTE
The status bits s68 to s71 are active H, unless the hardware pins a 1
in these bits always indicates successful lock.
4.2.2.1.2 TPS Index Register ($09, W)
The function of this register is twofold: Writing a value in the allowed range (0 to 8) stops
automatic updates to the TPS data. The number of bytes to read is determined from the value
written (x) according to 9 - x (a value of 0 corresponds to reading the complete TPS block of
9 bytes). The TPS bytes may be read in any order from arbitrary addresses but the specified
number must be read. As an example consider the reading of TPS registers 0, 4 and 8:
Write 6 to address 9 (TPS index register): Stop automatic update and prepare for 3 bytes to read.
tion • Read address 0 -> TPS register 0.
a • Read address 8 -> TPS register 8.
• Read address 4 -> TPS register 4.
rm Note that the order of reading the 3 bytes is arbitrary. After reading
fo the 3rd byte automatic update of the TPS registers is enabled again.
In 4.2.2.1.3 Software Reset ($0A, W)
y Writing a sequence of 0 - 1 - 0 into this register issues a soft reset of the OFDM block. In this
r case all the internal control loops start again, but the internal values programmed into the
a registers are preserved.
in 4.2.2.1.4 OFDM Mode ($0B..$0D, R/W and W)
lim These registers hold the internal settings of the OFDM block for the modulation and the guard
e interval. The bit assignments are shown in Table 4-3 through Table 4-5, the initial value after
Pr reset is given by the annotation (i.v.).
Table 4-3. OFDM Register 0 ($0B, R/W)
CODERATE BIT[7:4]
0000: 1/2
0001: 2/3 (I.V.)
0010: 3/4
0011: 5/6
0100: 7/8
0101: RESERVED
0110: RESERVED
0111: RESERVED
1XXX: RESERVED
GUARD BIT[3:2
00: 1/32 (I.V.)
01: 1/16
10: 1/8
11: 1/4
CONST BIT[1:0]
00: QPSK
01: 16-QAM
10: 64-QAM (I.V.)
11: RESERVED
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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MOTOROLA
4-11