MC92314 Datasheet, PDF (24/100 Pages) Motorola, Inc – DVB-T Single Chip Demodulator Application Note

Device Description
Freescale Semiconductor, Inc.
3.2.3 FEC Block
The FEC block completes Motorola’s DVB-T single chip demodulator by providing all the FEC
functions necessary for the reception of DVB-T transmissions. It is fully compliant to the ETSI
specification for digital terrestrial broadcasting (see reference [1-1]).
VLCK
VFF VEF
SR2..0
G1DATA2..0
G2DATA2..0
VDCLK
Node
Synchroniser
FIFO
Depuncturing
Viterbi
Core
VO
DIVALID
SYMCLK
tion ^RESB
a _SERIALIN
ry ^{Inform RSONLY}
I²C Interface
SCL SDA
Check Byte
Generation
Deinterleav-
er Memory
and Address
Sequencer
Frame
Synchroniser
Error Detec-
tion and Evalu-
Code-
word
Delay
FIFO
Error Location
and Value Gener-
BITCLKOUT
RERRU
Descrambler for
Energy Dispersal
Removal
Frame Detection
SPO7..0
DOVALID
SVALO
INSYNC _FSTART
ina _{Figure 3-5. Block Diagram of the FEC Block}
lim 3.2.3.1 Node Synchroniser
e _{3.2.3.1.1 Syndrome Based Node Synchronisation}
Pr ^{Prior to producing valid data the Viterbi decoder block must synchronise to the input data stream,}
including removing any phase ambiguity in the received symbols and determine the punctured
code rate transmitted.
The Viterbi block employs a method known as Syndrome Based Node Synchronisation to
achieve both I & Q symbol and punctured rate Synchronisation. This method has certain
advantages over other more common Synchronisation methods such as observation of path
metric growth rates and re-encoding of the received data stream:
• Path metric growth observations are relatively sensitive to input magnitude variations and
require multiple estimation cycles to detect Synchronisation.
• Re-encoding of the data stream (using a convolutional encoder) requires multiple estimation
cycles and can increase the latency of the decoder.
MOTOROLA
3-6
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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