MC92314 Datasheet, PDF (25/100 Pages) Motorola, Inc – DVB-T Single Chip Demodulator Application Note

Freescale Semiconductor, Inc.
Device Description
Syndrome based node synchronisation is independent of the average input magnitude and can
also easily detect changes of the synchronisation state.
The theory is based on the observation that the product of the incoming data and a syndrome
(predetermined by simulation for each data rate) is zero if synchronised correctly. In any other
case, the probability of 0’s vs. 1’s in the product increases. In the extreme case, i.e. the node
synchronisation is completely wrong, the product is random and there is equiprobability of 0’s
and 1’s. This behaviour is exploited for syndrome based node synchronisation.
3.2.3.1.2 Synchronisation States
The possible states that the synchroniser has to deal with are a combination of the following
factors:
n _{• The phasing of the received symbols. The synchroniser must decide which of two possible}
tio ^{states the I and Q input streams are in. They can either be processed as-is or can be rotated}
90^o to account for constellation rotation in the receiver.
a _{• Determination of the framing of the I and Q bit streams so as to extract the correct symbol.}
rm ^{There are four possible ways to frame the two bit streams and the synchroniser must}
fo ^{determine the correct one.}
3.2.3.1.3 Synchroniser Parameters
In _{The synchroniser is based on an estimator which determines whether the received symbol}
y sequence is in the correct synchronisation state. This estimate is based on single sided
r _{sequential probability ratio tests (SPRTs). The tests are based on the accumulation of the log-}
a _{likelihood ratio (LLR) that a certain hypothesis (in-sync or out-of-sync) for the input sequence}
in holds. A vote for a hypothesis is obtained if the accumulated LLR reaches a certain threshold.
The accumulator value L is computed as shown in the flowchart in Figure .
lim _NOTE
Pre ^{If a vote for out-of-sync occurs, the synchronisation state (which is}
output at I²C register SYNCH_STATE) is increased to test the next
hypothesis.
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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