MC92314 Datasheet, PDF (73/100 Pages) Motorola, Inc – DVB-T Single Chip Demodulator Application Note

Freescale Semiconductor, Inc.
DVB-T Demodulator Interfaces
4.2.2.2.16 SOFT_RESET Register
Read -
Write
Access
7
6
5
4
3
R/W ^GP3
GP2
GP1
GP0
0
Default Setting After Reset:
0
0
0
0
0
I2C
2
1
0
Register
Address
FFT
RS
VIT _$1F
0
0
0
VIT
Writing the sequence of 0 - 1 - 0 into this bit initiates a soft-reset of the Viterbi decoder.
tion ^RS
a _{Like the VIT bit before this bit does a soft-reset of the RS decoder.}
rm _FFT
fo _{Like the VIT bit before this bit does a soft-reset of the FFT block.}
In _GP[3:0]
ry _{These bits set the logic levels at the general purpose output pins.}
ina _{4.3 Tuner Interface}
lim ^{The tuner is normally programmed by a microcontroller or the overall system processor via I2C}
interface. It must tune to the OFDM centre frequency of the desired VHF or UHF channel,
Pre ^{normally possible offsets are taken into account by the controller.}
The interface between the tuner and the DVB-T demodulator MC92314 consists of the following
signals:
• The overall DVB-T system clock of 256/7 ~ 36.57 MHz.
• Overall DVB-T system clock divided by 2 (128/7 ~ 18.28 MHz).
• 8 bit parallel ADC data (real only), positioned in the IF range using an IF of 32/7 MHz
• The VCXO control signal from the OFDM block.
• The AGC control signal from the OFDM block.
4.3.1 General Tuner Characteristics
To work in the appropriate way the tuner part of the DVB-T frontend has to meet the following
specifications:
• Noise figure: 6 dB typical. 8 dB worst case.
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
4-25