MC92314 Datasheet, PDF (49/100 Pages) Motorola, Inc – DVB-T Single Chip Demodulator Application Note

Freescale Semiconductor, Inc.
DVB-T Demodulator Interfaces
SECTION 4
DVB-T DEMODULATOR INTERFACES
Extensive control and insight into all relevant system parameters is given to the user of
Motorola’s single chip DVB-T demodulator by the interfaces of the IC. To control the actions of
the chip several status lines as well as internal registers are provided. The information presented
in this section describes the details of the external interfaces. Also all the information necessary
to understand the setup of the circuit as described in Section 5 is given.
According to the characteristics of the interfaces the description is separated into the (physical)
control lines and software controllable registers.
n _{4.1 General Purpose Outputs}
tio _{Four general purpose output pins are provided that can be set via the I}²_{C interface of the FEC}
a _{block. The corresponding bits reside in the 4 MSBs of the SOFT_RESET register (address $1F}
in the FEC block), these bits set the outputs of the GP[3:0] pins (pin numbers 104, 102, 99 and
rm 97) of the MC92314.
fo _{Possible applications include control of the DVB-T tuner. In some applications it may be useful}
In ^{to prevent the tuner interface from listening to the I2C communication all the time to keep the}
noise introduced by the digitial signals away from the analog circuitry of the tuner. This can easily
y _{be achieved by feeding the SDA and SCL lines to the tuner via analog switches that are enabled}
r _{by one of the general purpose outputs.}
ina _{Even in case of non-standardised serial tuner interfaces that need only input from the system}
controller the whole data transmission from the system controller to the tuner can be done by
lim ^{using these outputs.}
re _{4.2 I}²_{C Interface}
P _{Motorola’s M-Bus implemented in the device is functionally identical to the well-known I2C bus.}
It is a two wire serial and bidirectional interface for (comparatively) slow data transmission. In
many STB systems it is used to exchange control information between a host processor and
peripherals using only 2 package pins. The I²C bus consists of a clock (SCL) and a data (SDA)
signal. Both signals are bidirectional with open-drain output. Each device can send and receive
clock and data. The master of the bus generates the clock. Figure 4-1 demonstrates the
bidirectional open-drain bus configuration with 2 slaves and one master. The thick lines highlight
the data flow during a read transfer from Slave1 to the master.
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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4-1