MC92314 Datasheet, PDF (57/100 Pages) Motorola, Inc – DVB-T Single Chip Demodulator Application Note

Freescale Semiconductor, Inc.
DVB-T Demodulator Interfaces
Table 4-1. I2C Registers of the OFDM Block
Addr Name Type Def b7
b6
b5
b4
b3
b2
b1
b0
$0 TPS R0
R
-
S[7:0]
$1 TPS R1
R
-
S[15:8]
$2 TPS R2
R
-
S[23:16]
$3 TPS R3
R
-
S[31:24]
$4 TPS R4
R
-
S[39:32]
$5 TPS R5
R
-
S[47:40]
$6 TPS R 6
R
-
S[55:48]
$7 TPS R7
R
-
S[63:56]
$8
$9
$A
$B
$C
$D
$E
$F
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
TPS R 8
R
n TPS Idx
W
tio ^{Soft Reset}
W
OFDM R0
R/W
a _{OFDM R1}
W
m ^{OFDM R2}
W
r _{CLK Coeff}
R/W
fo ^{INT Gain Offs R/W}
In ^{AFC Strt 0}
R/W
AFC Strt 1
R/W
y _{AFC Thr 0}
R/W
r _{AFC Thr 1}
R/W
a _{AGC Thr}
R/W
in _{AFC Sw Sp 0 R/W}
lim ^{AFC Sw Sp 1 R/W}
CSE R0
R/W
e _{CSE R1}
R/W
Pr ^{CSE R2}
R/W
- AFCL CLKL TPSV TPSL
S[67:64]
-
IDX[7:0]
$00
SRES
$12
CODERATE
GUARD
CONST
$1C
00
0
1
ASYN ATPS AFC TSM
$75 FTSE AFCS AGCS
10
UHFI ADCM CLKS
$1F
PROPORTIONAL
INTEGRATOR
$EF
AGC Gain Offset
AFC Gain Offset
$00
AFCSTART[7:0]
$10
AFCSTART[15:8]
$13
AFCTHRESHOLD[7:0]
$10
AFCTHRESHOLD[15:8]
$1F
AGCTHRESHOLD[7:0]
$80
AFCSWEEPSPEED[7:0]
$00
AFCSWEEPSPEED[15:8]
$C5
CSE[7:0]
$D2
CSE[15:8]
$DF
CSE[23:16]
$1A CSE R3
R/W $10S
CSE[31:24]
$21 Internal
W $FA
1
1
1
1
1
0
1
0
$25 AGC Fix 0
W $00
AGCFIX[7:0]
$26 AGC Fix 1
W $00
0000
AGCFIX[11:8]
$2F AFC Fdbk 0
R
-
AFCFEEDBACK[7:0]
$30 AFC Fdbk 1
R
-
AFCFEEDBACK[15:8]
$33 AGC Fdbk 0 R
-
AGCFEEDBACK[7:0]
$34 AGC Fdbk 1 R
-
0000
AGCFEEDBACK[11:8]
$36 VCXO Fix 0 W $00
VCXOFIX[7:0]
$37 VCXO Fix 1 W $00
0000
VCXOFIX[11:0]
4.2.2.1.1 TPS Registers 0 - 8 ($00..$08, R)
According to the DVB-T specification (see reference [1-1]) the TPS data are decoded inside of
the OFDM block. These data are stored in the first 68 bits of the TPS registers. The remaining
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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