MT40A512M16HA-083EIT Datasheet, PDF (78/373 Pages) Micron Technology – Programmable data strobe preambles

8Gb: x4, x8, x16 DDR4 SDRAM
Write Leveling
The figure below is another representative way to view the write leveling procedure. Al-
though it shows the clock varying to a static strobe, this is for illustrative purpose only;
the clock does not actually change phase, the strobe is what actually varies. By issuing
multiple WL bursts, the DQS strobe can be varied to capture with fair accuracy the time
at which the clock edge arrives at the DRAM clock input buffer.
Figure 22: Write Leveling Concept, Example 2
CK_c
CK_t
CK_c
CK_t
CK_c
CK_t
DQS_t/
DQS_c
t_WLS
111 11111 11 111 1111 1
t_WLH
0 000 000 000 000
t_WLS t_WLH
0 0 0 0 0 0 0 _{X XX XXX} 11 111 1111 1
t_WLO
DQ (CK 0 to 1)
DQ (CK 1 to 0)
DRAM Setting for Write Leveling and DRAM TERMINATION Function in that Mode
The DRAM enters into write leveling mode if A7 in MR1 is HIGH. When leveling is fin-
ished, the DRAM exits write leveling mode if A7 in MR1 is LOW (see the MR Leveling
Procedures table). Note that in write leveling mode, only DQS terminations are activa-
ted and deactivated via the ODT pin, unlike normal operation (see DRAM DRAM TER-
MINATION Function in Leveling Mode table).
Table 25: MR Settings for Leveling Procedures
Function
Write leveling enable
Output buffer mode (Q off)
MR1
A7
A12
Enable
1
0
Disable
0
1
Table 26: DRAM TERMINATION Function in Leveling Mode
ODT Pin at DRAM
R_TT(NOM) with ODT HIGH
DQS_t/DQS_c Termination
On
DQ Termination
Off
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8gb_ddr4_dram.pdf - Rev. G 1/17 EN
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