MT40A512M16HA-083EIT Datasheet, PDF (100/373 Pages) Micron Technology – Programmable data strobe preambles

8Gb: x4, x8, x16 DDR4 SDRAM
Multipurpose Register
Figure 41: READ-to-REFRESH Timing
T0
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Ta8
Ta9
CK_c
CK_t
Command READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
REF²
DES
DES
Address Add¹
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
CKE
BL = 8
DQS_t, DQS_c
DQ
BC = 4
DQS_t, DQS_c
DQ
PL + AL + CL
(4 + 1) + Clocks
UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7
UI0 UI1 UI2 UI3
t_RFC
Time Break
Don’t Care
Notes:
1. Address setting:
A[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here)
A2 = 0b (for BL = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7)
BA1 and BA0 indicate the MPR location
A10 and other address pins are "Don’t Care," including BG1 and BG0. A12 is "Don’t
Care" when MR0 A[1:0] = 00 or 10, and must be 1b when MR0 A[1:0] = 01
2. 1x refresh is only allowed when MPR mode is enabled.
Figure 42: WRITE-to-REFRESH Timing
T0
CK_c
CK_t
T1
Ta0
Ta1
Ta2
Command WRITE
Address Add¹
DES
Valid
DES
t_{WR_MPR}
Valid
DES
Valid
REF²
Valid
Ta3
DES
Valid
Ta4
DES
Valid
Ta5
Ta6
DES
DES
t_RFC
Valid
Valid
Ta7
DES
Valid
Ta8
DES
Valid
Ta9
DES
Valid
Ta10
DES
Valid
CKE
DQS_t,
DQS_c
DQ
Notes: 1. Address setting:
BA1 and BA0 indicate the MPR location
Time Break
Don’t Care
09005aef861d1d4a
8gb_ddr4_dram.pdf - Rev. G 1/17 EN
100
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