MT40A512M16HA-083EIT Datasheet, PDF(317/373 Page) Micron Technology – Programmable data strobe preambles

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MT40A512M16HA-083EIT Datasheet, PDF (317/373 Pages) Micron Technology – Programmable data strobe preambles

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8Gb: x4, x8, x16 DDR4 SDRAM

Current Specifications â Measurement Conditions

Table 136: Basic IDD, IPP, and IDDQ Measurement Conditions (Continued)

Symbol

IDD7

IPP7

IDD8

Description

Operating Bank Interleave Read Current

CKE: HIGH; External clock: on; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see the previous table; BL: 8;15 AL: CL -

1; CS_n: HIGH between ACT and RDA; Command, address, group bank adress, bank address inputs: partially

toggling according to the IDD7 Measurement-Loop Pattern table; Data I/O: read data bursts with different data

between one burst and the next one according to the IDD7 Measurement-Loop Pattern table; DM: stable at 1;

Bank activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see the IDD7

Measurement-Loop Pattern table; Output buffer and RTT: enabled in mode registers;2 ODT signal: stable at 0;

Pattern details: see the IDD7 Measurement-Loop Pattern table

Operating Bank Interleave Read IPP Current

Same conditions as IDD7 above

Maximum Power Down Current

Place DRAM in MPSM then CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n:

stable at 1; Command, address, bank group address, bank address inputs: stable at 0; Data I/O: VDDQ; DM_n:

stable at 1; Bank activity: all banks closed; Output buffer and RTT: Enabled in mode registers;2 ODT signal: sta-

ble at 0

Notes:

1. Burst length: BL8 fixed by MRS: set MR0[1:0] 00.

2. Output buffer enable: set MR1[12] 0 (output buffer enabled); set MR1[2:1] 00 (RON =

RZQ/7); RTT(NOM) enable: set MR1[10:8] 011 (RZQ/6); RTT(WR) enable: set MR2[11:9] 001

(RZQ/2), and RTT(Park) enable: set MR5[8:6] 000 (disabled).

3. Auto self refresh (ASR): set MR2[6] 0 to disable or MR2[6] 1 to enable feature.

4. Self refresh temperature range (SRT): set MR2[7] 0 for normal or MR2[7] 1 for extended

temperature range.

5. READ burst type: Nibble sequential, set MR0[3] 0.

09005aef861d1d4a

8gb_ddr4_dram.pdf - Rev. G 1/17 EN

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Micron Technology, Inc. reserves the right to change products or specifications without notice.

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