MT40A512M16HA-083EIT Datasheet, PDF (280/373 Pages) Micron Technology – Programmable data strobe preambles

8Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics – AC and DC Differential Input Meas-
urement Levels
3. These values are not defined; however, the differential signals (CK_t, CK_c) need to be
within the respective limits, V_IH(DC)max and V_IL(DC)min for single-ended signals as well as
the limitations for overshoot and undershoot.
Table 99: Minimum Time AC Time ^tDVAC for CK
Slew Rate (V/ns)
>4.0
4.0
3.0
2.0
1.9
1.6
1.4
1.2
1.0
<1.0
t_{DVAC (ps) at |VIH,diff(AC) to VIL,diff(AC)|}
200mV
TBDmV
120
TBD
115
TBD
110
TBD
105
TBD
100
TBD
95
TBD
90
TBD
85
TBD
80
TBD
80
TBD
Note: 1. Below V_IL(AC).
Single-Ended Requirements for CK Differential Signals
Each individual component of a differential signal (CK_t, CK_c) has to comply with cer-
tain requirements for single-ended signals. CK_t and CK_c have to reach approximately
V_SEHmin/V_SEL,max, which are approximately equal to the AC levels V_IH(AC) and V_IL(AC) for
ADD/CMD signals in every half-cycle. The applicable AC levels for ADD/CMD might
differ per speed-bin, and so on. For example, if a value other than 100mV is used for
ADD/CMD V_IH(AC) and V_IL(AC) signals, then these AC levels also apply for the single-
ended signals CK_t and CK_c.
While ADD/CMD signal requirements are with respect to V_REFCA, the single-ended com-
ponents of differential signals have a requirement with respect to V_DD/2; this is nomi-
nally the same. The transition of single-ended signals through the AC levels is used to
measure setup time. For single-ended components of differential signals the require-
ment to reach V_SEL,max/V_SEH,min has no bearing on timing, but adds a restriction on the
common mode characteristics of these signals.
09005aef861d1d4a
8gb_ddr4_dram.pdf - Rev. G 1/17 EN
280
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