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| MT40A512M16HA-083EIT Datasheet, PDF (41/373 Pages) Micron Technology – Programmable data strobe preambles | |||
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8Gb: x4, x8, x16 DDR4 SDRAM
RESET and Initialization Procedure
Figure 15: RESET Procedure at Power Stable Condition
Ta
Tb
Tc
Td
Te
Tf
Tg
Th
Ti
CK_t, CK_c
tCKSRX
VPP
VDD, VDDQ
RESET_n
CKE
Command
tPW_RESET_S
T = 500μs
tIS
T (MIN) = 10ns
tIS
tXPR
tMRD
tMRD
tMRD
tDLLK
tMOD
Note 1
MRS
MRS
MRS
MRS
ZQCL
Tj
tZQinit
Note 1
Tk
Valid
Valid
BG, BA
ODT
MRx
MRx
MRx
MRx
tIS
Static LOW in case RTT(NOM) is enabled at time Tg, otherwise static HIGH or LOW
Valid
tIS
Valid
RTT
Time Break
Donât Care
Notes:
1. From time point Td until Tk, a DES command must be applied between MRS and ZQCL
commands.
2. MRS commands must be issued to all mode registers that have defined settings.
3. In general, there is no specific sequence for setting the MRS locations (except for de-
pendent or co-related features, such as ENABLE DLL in MR1 prior to RESET DLL in MR0,
for example).
4. TEN is not shown; however, it is assumed to be held LOW.
Uncontrolled Power-Down Sequence
In the event of an uncontrolled ramping down of VPP supply, VPP is allowed to be less
than VDD provided the following conditions are met:
⢠Condition A: VPP and VDD/VDDQ are ramping down (as part of turning off ) from nor-
mal operating levels.
⢠Condition B: The amount that VPP may be less than VDD/VDDQ is less than or equal to
500mV.
⢠Condition C: The time VPP may be less than VDD is â¤10ms per occurrence with a total
accumulated time in this state â¤100ms.
09005aef861d1d4a
8gb_ddr4_dram.pdf - Rev. G 1/17 EN
41
Micron Technology, Inc. reserves the right to change products or specifications without notice.
 2015 Micron Technology, Inc. All rights reserved.
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