MT40A512M16HA-083EIT Datasheet, PDF (218/373 Pages) Micron Technology – Programmable data strobe preambles

8Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
Figure 160: READ (BC4: Fixed) to WRITE (BC4: Fixed) with 1^tCK Preamble and Write CRC in Same or
Different Bank Group
T0
T1
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
CK_c
CK_t
Command READ
DES
DES
WRITE
DES
Bank Group
Address
READ to WRITE command delay
= RL +BL/2 - WL + 2 ^tCK
BGa
BGa or
BGb
Address
Bank
Col n
Bank
Col b
DES
DES
DQS_t,
DQS_c
DQ x4,
BC = 4 (Fixed)
DQ x8/X16,
BC = 4 (Fixed)
RL = 11
WL = 9
DES
DES
DES
DES
DES
DES
DES
DES
2 Clocks
t_RPRE
t_RPST
t_WPRE
DO DO DO DO
n n+1 n+2 n+3
DO DO DO DO
n n+1 n+2 n+3
DI DI DI DI
b b+1 b+2 b+3
DI DI DI DI
b b+1 b+2 b+3
DES
DES
DES
t_WR
t_WTR
t_WPST
CRC CRC
CRC
Time Break
Transitioning Data
Don’t Care
Notes:
1. BC = 4 (Fixed), RL = 11 (CL = 11, AL = 0), READ preamble = 1^tCK, WL = 9 (CWL = 9, AL =
0), WRITE preamble = 1^tCK.
2. DO n = data-out from column n, DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 10.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Enable.
READ Operation with Command/Address Latency (CAL) Enabled
Figure 161: Consecutive READ (BL8) with CAL (3^tCK) and 1^tCK Preamble in Different Bank Group
T0
CK_c
CK_t
Command
w/o CS_n
CS_n
Bank Group
Address
T1
T2
T3
T4
T5
T6
T7
T8
T13
T14
T15
T17
T18
T19
T21
T22
T23
t_{CAL = 3}
t_{CAL = 3}
DES
DES
READ
DES
DES
DES
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
t_{CCD_S = 4}
BGa
BGb
Address
DQS_t,
DQS_c
DQ
Bank
Col n
Bank
Col b
RL = 11
t_RPRE
t_RPST
RL = 11
DI DI DI DI DI DI DI DI DI DI DI DI
n n+1 n+2 n+5 n+6 n+7 b b+1 b+2 b+5 b+6 b+7
Notes: 1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 1^tCK.
Time Break
Transitioning Data
Don’t Care
09005aef861d1d4a
8gb_ddr4_dram.pdf - Rev. G 1/17 EN
218
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