MT40A512M16HA-083EIT Datasheet, PDF (184/373 Pages) Micron Technology – Programmable data strobe preambles

8Gb: x4, x8, x16 DDR4 SDRAM
Programmable Preamble Modes and DQS Postambles
READ Preamble Mode
MR4[11] = 0 selects 1^tCK READ preamble mode and MR4[11] = 1 selects 2^tCK READ pre-
amble mode. Examples are shown in the following figure.
Figure 113: 1^tCK vs. 2^tCK READ Preamble Mode
1^tCK Mode
RD
CK_c
CK_t
DQS_t,
DQS_c
CL
Preamble
DQ
2^tCK Mode
RD
CK_c
CK_t
DQS_t,
DQS_c
D0 D1 D2 D3 D4 D5 D6 D7
CL
Preamble
DQ
D0 D1 D2 D3 D4 D5 D6 D7
READ Preamble Training
DDR4 supports READ preamble training via MPR reads; that is, READ preamble train-
ing is allowed only when the DRAM is in the MPR access mode. The READ preamble
training mode can be used by the DRAM controller to train or "read level" its DQS re-
ceivers. READ preamble training is entered via an MRS command (MR4[10] = 1 is ena-
bled and MR4[10] = 0 is disabled). After the MRS command is issued to enable READ
preamble training, the DRAM DQS signals are driven to a valid level by the time ^tSDO is
satisfied. During this time, the data bus DQ signals are held quiet, that is, driven HIGH.
The DQS_t signal remains driven LOW and the DQS_c signal remains driven HIGH until
an MPR Page0 READ command is issued (MPR0 through MPR3 determine which pat-
tern is used), and when CAS latency (CL) has expired, the DQS signals will toggle nor-
mally depending on the burst length setting. To exit READ preamble training mode, an
MRS command must be issued, MR4[10] = 0.
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8gb_ddr4_dram.pdf - Rev. G 1/17 EN
184
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