MT40A512M16HA-083EIT Datasheet, PDF (343/373 Pages) Micron Technology – Programmable data strobe preambles

8Gb: x4, x8, x16 DDR4 SDRAM
Speed Bin Tables
Table 155: DDR4-2666 Speed Bins and Operating Conditions (Continued)
DDR4-2666 Speed Bin
CL-nRCD-nRP
Parameter
Supported CL settings
Supported CL settings with read DBI
Supported CWL settings
-075F
-075E
-075
17-17-17
18-18-18
19-19-19
Symbol Min
Max
Min
Max
Min
Max Unit
9–20
9–20
10,12-–20
nCK
11–16, 18–23
11–16, 18–23
12, 14–16, 18–23 nCK
9, 10, 11, 12, 14, 16, 9, 10, 11, 12, 14, 16, 9, 10, 11, 12, 14, 16, nCK
18
18
18
Notes:
1. Speed Bin table is only valid with DLL enabled and gear-down mode disabled.
2. When operating in 2^tCK WRITE preamble mode, CWL must be programmed to a value
at least 1 clock greater than the lowest CWL setting supported in the applicable ^tCK
range.
3. The programmed value of CWL must be less than or equal to programmed value of CL.
4. ^tCK (AVG) MIN.
5. The DRAM supports 13.92ns with CL13 operation, 14.07ns with CL15 operation, and
14.16ns with CL17 operation at defined clock rates.
6. If the clock period is less than 0.938ns and greater than or equal to 0.937ns, timing pa-
rameters that are derived off the clock will use 0.938ns as its reference. For example, if
t_{CK (MIN) = 0.938ns and} t_{RP = 14.06ns, then} t_{RP would require 15nCKs (14.06ns/}
0.938ns), but if ^tCK (MIN) = 0.937ns and ^tRP = 14.06ns, then ^tRP would still require
15nCKs (14.06ns/ 0.938ns) and not 16nCKs (14.06ns/ 0.937ns).
7. When calculating ^tRC and ^tRP in clocks, values may not be used in a combination that
would violate ^tRAS.
Table 156: DDR4-2933 Speed Bins and Operating Conditions
DDR4-2933 Speed Bin
CL-nRCD-nRP
Parameter
Internal READ command to first data
Internal READ command to first data
with read DBI enabled
Symbol
t_AA
t_{AA_DBI}
ACTIVATE to internal READ or WRITE
delay time
PRECHARGE command period
ACTIVATE-to-PRECHARGE command
period
ACTIVATE-to-ACTIVATE or REFRESH
command period
READ: READ: DBI WRITE
nonDBI
CL = 9 CL = 11
CWL = 9
CL = 10 CL = 12
CWL = 9
CL = 10 CL = 12
CWL = 9, 11
t_RCD
t_RP
t_RAS
t_RC6
Symbol
t_CK4
t_CK4
t_CK4
-068E
20-20-20
Min
Max
13.64⁵ 19.00
t_AA
(MIN) +
4nCK
t_AA
(MAX) +
4nCK
13.64
–
13.64
32
–
9 × ^tREFI
t_{RAS +}
t_RP
Min
–
Max
1.5
1.9
1.5
1.9
Reserved
-068
21-21-21
Min
Max
14.32
19.00
t_AA
(MIN) +
4nCK
t_AA
(MAX) +
4nCK
14.32
–
14.32
32
–
9 × ^tREFI
t_{RAS +}
t_RP
Min
–
Max
Reserved
1.5
1.9
Reserved
-068D
22-22-22
Min
Max
15
19.00
t_AA
(MIN) +
4nCK
t_AA
(MAX) +
4nCK
15
–
Unit
ns
ns
ns
15
–
ns
32
9 × ^tREFI ns
t_{RAS +}
t_RP
Min
–
ns
Max Unit
Reserved
ns
1.5
1.9
ns
Reserved
ns
09005aef861d1d4a
8gb_ddr4_dram.pdf - Rev. G 1/17 EN
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