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MT40A512M16HA-083EIT Datasheet, PDF (128/373 Pages) Micron Technology – Programmable data strobe preambles
8Gb: x4, x8, x16 DDR4 SDRAM
Connectivity Test Mode
Table 39: Connectivity Mode Pin Description and Switching Levels
CT Mode
Pins
Pin Name During Normal Memory Operation
Test enable TEN
Chip select CS_n
Test
input
BA[1:0], BG[1:0], A[9:0], A10/AP, A11, A12/BC_n, A13, WE_n/A14,
A CAS_n/A15, RAS_n/A16, CKE, ACT_n, ODT, CLK_t, CLK_c, PAR
B LDM_n/LDBI_n, UDM_n/UDBI_n; DM_n/DBI_n
C ALERT_n
D RESET_n
Test
output
DQ[15:0], UDQS_t, UDQS_c, LDQS_t, LDQS_c; DQS_t, DQS_c
Switching Level
CMOS (20%/80% VDD)
VREFCA ±200mV
VREFCA ±200mV
VREFDQ ±200mV
CMOS (20%/80% VDD)
CMOS (20%/80% VDD)
VTT ±100mV
Notes
1, 2
3
3
4
2, 5
2
6
Notes:
1. TEN: Connectivity test mode is active when TEN is HIGH and inactive when TEN is LOW.
TEN must be LOW during normal operation.
2. CMOS is a rail-to-rail signal with DC HIGH at 80% and DC LOW at 20% of VDD (960mV
for DC HIGH and 240mV for DC LOW.)
3. VREFCA should be VDD/2.
4. VREFDQ should be VDDQ/2.
5. ALERT_n switching level is not a final setting.
6. VTT should be set to VDD/2.
Minimum Terms Definition for Logic Equations
The test input and output pins are related by the following equations, where INV de-
notes a logical inversion operation and XOR a logical exclusive OR operation:
MT0 = XOR (A1, A6, PAR)
MT1 = XOR (A8, ALERT_n, A9)
MT2 = XOR (A2, A5, A13)
MT3 = XOR (A0, A7, A11)
MT4 = XOR (CK_c, ODT, CAS_n/A15)
MT5 = XOR (CKE, RAS_n/A16, A10/AP)
MT6 = XOR (ACT_n, A4, BA1)
MT7 = x16: XOR (DMU_n/DBIU_n , DML_n/DBIL_n, CK_t)
= x8: XOR (BG1, DML_n/DBIL_n, CK_t)
= x4: XOR (BG1, CK_t)
MT8 = XOR (WE_n/A14, A12 / BC, BA0)
MT9 = XOR (BG0, A3, RESET_n and TEN)
Logic Equations for a x4 Device, When Supported
DQ0 = XOR (MT0, MT1)
DQ1 = XOR (MT2, MT3)
DQ2 = XOR (MT4, MT5)
DQ3 = XOR (MT6, MT7)
DQS_t = MT8
DQS_c = MT9
09005aef861d1d4a
8gb_ddr4_dram.pdf - Rev. G 1/17 EN
128
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