N25Q512A13GF840E Datasheet, PDF (72/91 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q512A

512Mb, Multiple I/O Serial Flash Memory
XIP Mode
Figure 37: XIP Mode Directly After Power-On
C
t_{VSI (<100µ)}
V_CC
NVCR check:
XIP enabled
S#
DQ0
Mode 3
Mode 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A[MIN]
Xb
LSB
D_OUT D_OUT D_OUT D_OUT D_OUT
DQ[3:1]
A[MAX]
D_OUT D_OUT D_OUT D_OUT D_OUT
MSB
Dummy cycles
Note: 1. Xb is the XIP confirmation bit and should be set as follows: 0 to keep XIP state; 1 to exit
XIP mode and return to standard read mode.
Confirmation Bit Settings Required to Activate or Terminate XIP
The XIP confirmation bit setting activates or terminates XIP after it has been enabled or
disabled. This bit is the value on DQ0 during the first dummy clock cycle in the FAST
READ operation. In dual I/O XIP mode, the value of DQ1 during the first dummy clock
cycle after the addresses is always "Don't Care." In quad I/O XIP mode, the values of
DQ3, DQ2, and DQ1 during the first dummy clock cycle after the addresses are always
"Don't Care."
Table 31: XIP Confirmation Bit
Bit Value
0
1
Description
Activates XIP: While this bit is 0, XIP remains activated.
Terminates XIP: When this bit is set to 1, XIP is terminated and the device returns
to SPI.
Table 32: Effects of Running XIP in Different Protocols
Protocol
Extended I/O and Dual I/O
Dual I/O
Effect
In a device with a dedicated part number where RST# is enabled, a LOW pulse
on that pin resets XIP and the device to the state it was in previous to the last
power-up, as defined by the nonvolatile configuration register.
Values of DQ1 during the first dummy clock cycle are "Don't Care."
PDF: 09005aef84752721
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN
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