N25Q512A13GF840E Datasheet, PDF(71/91 Page) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q512A

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N25Q512A13GF840E Datasheet, PDF (71/91 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q512A

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512Mb, Multiple I/O Serial Flash Memory

XIP Mode

Execute-in-place (XIP) mode allows the memory to be read by sending an address to the

device and then receiving the data on one, two, or four pins in parallel, depending on

the customer requirements. XIP mode offers maximum flexibility to the application,

saves instruction overhead, and reduces random access time.

Activate or Terminate XIP Using Volatile Configuration Register

Applications that boot in SPI and must switch to XIP use the volatile configuration reg-

ister. XIP provides faster memory READ operations by requiring only an address to exe-

cute, rather than a command code and an address.

To activate XIP requires two steps. First, enable XIP by setting volatile configuration reg-

ister bit 3 to 0. Next, drive the XIP confirmation bit to 0 during the next FAST READ op-

eration. XIP is then active. Once in XIP, any command that occurs after S# is toggled re-

quires only address bits to execute; a command code is not necessary, and device oper-

ations use the SPI protocol that is enabled. XIP is terminated by driving the XIP confir-

mation bit to 1. The device automatically resets volatile configuration register bit 3 to 1.

Note: For devices with basic XIP, indicated by a part number feature set digit of 2 or 4, it

is not necessary to set the volatile configuration register bit 3 to 0 to enable XIP. Instead,

it is enabled by setting the XIP confirmation bit to 0 during the first dummy clock cycle

after any FAST READ command.

Activate or Terminate XIP Using Nonvolatile Configuration Register

Applications that must boot directly in XIP use the nonvolatile configuration register. To

enable a device to power-up in XIP using the nonvolatile configuration register, set non-

volatile configuration register bits [11:9]. Settings vary according to protocol, as ex-

plained in the Nonvolatile Configuration Register section. Because the device boots di-

rectly in XIP, after the power cycle, no command code is necessary. XIP is terminated by

driving the XIP confirmation bit to 1.

PDF: 09005aef84752721

n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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