N25Q512A13GF840E Datasheet, PDF (68/91 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q512A

512Mb, Multiple I/O Serial Flash Memory
ONE-TIME PROGRAMMABLE Operations
ONE-TIME PROGRAMMABLE Operations
READ OTP ARRAY Command
To initiate a READ OTP ARRAY command, S# is driven LOW. The command code is in-
put on DQ0, followed by address bytes and dummy clock cycles. Each address bit is
latched in during the rising edge of C. Data is shifted out on DQ1, beginning from the
specified address and at a maximum frequency of ^fC (MAX) on the falling edge of the
clock. The address increments automatically to the next address after each byte of data
is shifted out. There is no rollover mechanism; therefore, if read continuously, after lo-
cation 0x40, the device continues to output data at location 0x40. The operation is ter-
minated by driving S# HIGH at any time during data output.
Figure 35: READ OTP Command
Extended
C
DQ0
0
Command
MSB
7
8
LSB
A[MAX]
DQ1
High-Z
Dual
C
DQ[1:0]
0
Command
MSB
3
4
LSB
A[MAX]
Quad
C
DQ[3:0]
0
Command
MSB
1
2
LSB
A[MAX]
C_x
A[MIN]
D_OUT
MSB
D_OUT
D_OUT
Dummy cycles
C_x
A[MIN]
Dummy cycles
C_x
D_OUT
MSB
D_OUT
D_OUT
A[MIN]
Dummy cycles
D_OUT
MSB
LSB
D_OUT
D_OUT
D_OUT
D_OUT
D_OUT
LSB
D_OUT
D_OUT
D_OUT
LSB
D_OUT
D_OUT
Don’t Care
Note:
1. For extended SPI protocol, C_x = 7 + (A[MAX] + 1).
For dual SPI protocol, C_x = 3 + (A[MAX] + 1)/2.
For quad SPI protocol, C_x = 1 + (A[MAX] + 1)/4.
PROGRAM OTP ARRAY Command
To initiate the PROGRAM OTP ARRAY command, the WRITE ENABLE command must
be issued to set the write enable latch bit to 1; otherwise, the PROGRAM OTP ARRAY
command is ignored and flag status register bits are not set. S# is driven LOW and held
LOW until the eighth bit of the last data byte has been latched in, after which it must be
driven HIGH. The command code is input on DQ0, followed by address bytes and at
least one data byte. Each address bit is latched in during the rising edge of the clock.
When S# is driven HIGH, the operation, which is self-timed, is initiated; its duration is
t_{POTP. There is no rollover mechanism; therefore, after a maximum of 65 bytes are}
latched in the subsequent bytes are discarded.
PDF: 09005aef84752721
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN
68
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