N25Q512A13GF840E Datasheet, PDF (31/91 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q512A

512Mb, Multiple I/O Serial Flash Memory
READ REGISTER and WRITE REGISTER Operations
READ REGISTER and WRITE REGISTER Operations
READ STATUS REGISTER or FLAG STATUS REGISTER Command
To initiate a READ STATUS REGISTER command, S# is driven LOW. For extended SPI
protocol, the command code is input on DQ0, and output on DQ1. For dual SPI proto-
col, the command code is input on DQ[1:0], and output on DQ[1:0]. For quad SPI proto-
col, the command code is input on DQ[3:0], and is output on DQ[3:0]. The operation is
terminated by driving S# HIGH at any time during data output.
The status register can be read continuously and at any time, including during a PRO-
GRAM, ERASE, or WRITE operation.
The flag status register can be read continuously and at any time, including during an
ERASE or WRITE operation.
If one of these operations is in progress, checking the write in progress bit or program or
erase controller bit is recommended before executing the command.
The flag status register must be read any time a PROGRAM, ERASE, or SUSPEND/
RESUME command is issued, or after a RESET command while device is busy. The cycle
is not complete until bit 7 of the flag status register outputs 1. Refer to Command Defi-
nitions for more information.
The end of operations such as power-up, WRITE STATUS REGISTER, and WRITE NON-
VOLATILE CONFIGURATION REGISTER can be detected by means of a READ FLAG STA-
TUS REGISTER command being issued twice to poll the flag status register for both die,
S# toggled between command execution, and bit 7 of the flag status register outputs 1
both times.
PDF: 09005aef84752721
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN
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