N25Q512A13GF840E Datasheet, PDF (53/91 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q512A

512Mb, Multiple I/O Serial Flash Memory
PROGRAM Operations
PROGRAM Operations
PROGRAM commands are initiated by first executing the WRITE ENABLE command to
set the write enable latch bit to 1. S# is then driven LOW and held LOW until the eighth
bit of the last data byte has been latched in, after which it must be driven HIGH. The
command code is input on DQ0, followed by input on DQ[n] of address bytes and at
least one data byte. Each address bit is latched in during the rising edge of the clock.
When S# is driven HIGH, the operation, which is self-timed, is initiated; its duration is
t_PP.
If the bits of the least significant address, which is the starting address, are not all zero,
all data transmitted beyond the end of the current page is programmed from the start-
ing address of the same page. If the number of bytes sent to the device exceed the maxi-
mum page size, previously latched data is discarded and only the last maximum page-
size number of data bytes are guaranteed to be programmed correctly within the same
page. If the number of bytes sent to the device is less than the maximum page size, they
are correctly programmed at the specified addresses without any effect on the other
bytes of the same page.
When the operation is in progress, the program or erase controller bit of the flag status
register is set to 0. The write enable latch bit is cleared to 0, whether the operation is
successful or not. The status register and flag status register can be polled for the opera-
tion status. The operation is considered complete after bit 7 of the flag status register
outputs 1 with at least one byte output. When the operation completes, the program or
erase controller bit is cleared to 1.
If the operation times out, the write enable latch bit is reset and the program fail bit is
set to 1. If S# is not driven HIGH, the command is not executed, flag status register error
bits are not set, and the write enable latch remains set to 1. When a command is applied
to a protected sector, the command is not executed, the write enable latch bit remains
set to 1, and flag status register bits 1 and 4 are set.
Note that the flag status register must be polled even if operation times out.
Table 27: Data/Address Lines for PROGRAM Commands
Note 1 applies to entire table
Command Name
PAGE PROGRAM
DUAL INPUT FAST PROGRAM
EXTENDED DUAL INPUT
FAST PROGRAM
QUAD INPUT FAST PROGRAM
EXTENDED QUAD INPUT
FAST PROGRAM
Data In
DQ0
DQ[1:0]
DQ[1:0]
DQ[3:0]
DQ[3:0]
Address In
DQ0
DQ0
DQ[1:0]
DQ0
DQ[3:0]
Extended
Yes
Yes
Yes
Yes
Yes
Dual
Yes
Yes
Yes
No
No
Quad
Yes
No
No
Yes
Yes
Note: 1. Yes in the protocol columns indicates that the command is supported and has the same
functionality and command sequence as other commands marked Yes.
PDF: 09005aef84752721
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN
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