N25Q512A13GF840E Datasheet, PDF (24/91 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q512A

512Mb, Multiple I/O Serial Flash Memory
Nonvolatile and Volatile Registers
Table 15: Extended Address Register Bit Definitions
Note 1 applies to entire table
Bit Name
Settings
7 A[31:26]
0 = Reserved
6
5
4
3
2
1 A[25:24]
0
11 = Upper 128Mb segment
10 = Third 128Mb segment
01 = Second 128Mb segment
00 = Lower 128Mb segment (default)
Description
–
Enable selecting 128Mb segmentation. For A[25:24] ,
the default setting is determined by bit 1 of the non-
volatile configuration register. However, this setting
can be changed using the WRITE EXTENDED AD-
DRESS REGISTER command.
Note:
1. The extended address register is for an application that supports only 3-byte addressing.
It extends the device's first three address bytes A[23:0] to a fourth address byte A[31:24]
to enable memory access beyond 128Mb. The extended address register bits [1:0] are
used to select one of the four 128Mb segments of the memory array. If 4-byte address-
ing is enabled, extended address register settings are ignored.
Enhanced Volatile Configuration Register
Table 16: Enhanced Volatile Configuration Register Bit Definitions
Note 1 applies to entire table
Bit Name
7
Quad I/O protocol
6
Dual I/O protocol
5
Reserved
4
Reset/hold
3
V_PP accelerator
Settings
Description
0 = Enabled
Enables or disables quad I/O protocol.
1 = Disabled (Default,
extended SPI protocol)
0 = Enabled
Enables or disables dual I/O protocol.
1 = Disabled (Default,
extended SPI protocol)
x = Default
0b = Fixed value.
0 = Disabled
Enables or disables hold or reset.
1 = Enabled (Default) (Available on dedicated part numbers.)
0 = Enabled
1 = Disabled (Default)
Enables or disables V_PP acceleration for QUAD
INPUT FAST PROGRAM and QUAD INPUT EX-
TENDED FAST PROGRAM OPERATIONS.
Notes
2
2
PDF: 09005aef84752721
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN
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