N25Q512A13GF840E Datasheet, PDF (22/91 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q512A

512Mb, Multiple I/O Serial Flash Memory
Nonvolatile and Volatile Registers
Table 12: Sequence of Bytes During Wrap
Starting Address
0
1
15
31
63
16-Byte Wrap
0-1-2- . . . -15-0-1- . .
1-2- . . . -15-0-1-2- . .
15-0-1-2-3- . . . -15-0-1- . .
31-16-17- . . . -31-16-17- . .
63-48-49- . . . -63-48-49- . .
32-Byte Wrap
0-1-2- . . . -31-0-1- . .
1-2- . . . -31-0-1-2- . .
15-16-17- . . . -31-0-1- . .
31-0-1-2-3- . . . -31-0-1- . .
63-32-33- . . . -63-32-33- . .
64-Byte Wrap
0-1-2- . . . -63-0-1- . .
1-2- . . . -63-0-1-2- . .
15-16-17- . . . -63-0-1- . .
31-32-33- . . . -63-0-1- . .
63-0-1- . . . -63-0-1- . .
Table 13: Supported Clock Frequencies – STR
Note 1 applies to entire table
Number of Dummy
Clock Cycles
1
2
3
4
5
6
7
8
9
10
FAST READ
90
100
108
108
108
108
108
108
108
108
DUAL OUTPUT
FAST READ
80
90
100
105
108
108
108
108
108
108
DUAL I/O FAST
READ
50
70
80
90
100
105
108
108
108
108
QUAD OUTPUT
FAST READ
43
60
75
90
100
105
108
108
108
108
QUAD I/O FAST
READ
30
40
50
60
70
80
86
95
105
108
Note: 1. Values are guaranteed by characterization and not 100% tested in production.
Table 14: Supported Clock Frequencies – DTR
Note 1 applies to entire table
Number of Dummy
Clock Cycles
1
2
3
4
5
6
7
8
9
10
FAST READ
45
50
54
54
54
54
54
54
54
54
DUAL OUTPUT
FAST READ
40
45
50
53
54
54
54
54
54
54
DUAL I/O FAST
READ
25
35
40
45
50
53
54
54
54
54
QUAD OUTPUT
FAST READ
30
38
45
47
50
53
54
54
54
54
QUAD I/O FAST
READ
15
20
25
30
35
40
43
48
53
54
Note: 1. Values are guaranteed by characterization and not 100% tested in production.
PDF: 09005aef84752721
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN
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