N25Q512A13GF840E Datasheet, PDF (40/91 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q512A

512Mb, Multiple I/O Serial Flash Memory
READ IDENTIFICATION Operations
Figure 13: READ ID and MULTIPLE I/O Read ID Commands
Extended
C
DQ0
DQ1
Dual
C
DQ[1:0]
Quad
C
DQ[3:0]
0
7
8
15
16
31
32
Command
MSB
High-Z
0
LSB
D_OUT
MSB
LSB
D_OUT
D_OUT
MSB
LSB
D_OUT
D_OUT
MSB
LSB
D_OUT
Manufacturer
Device
UID
identification
identification
3
4
7
8
15
Command
MSB
LSB
D_OUT
MSB
LSB
D_OUT
D_OUT
MSB
LSB
D_OUT
Manufacturer
identification
Device
identification
0
1
2
3
4
7
Command
MSB
LSB
D_OUT
MSB
LSB
D_OUT
D_OUT
MSB
LSB
D_OUT
Manufacturer
identification
Device
identification
Don’t Care
Note: 1. The READ ID command is represented by the extended SPI protocol timing shown first.
The MULTIPLE I/O READ ID command is represented by the dual and quad SPI protocols
are shown below extended SPI protocol.
READ SERIAL FLASH DISCOVERY PARAMETER Command
To execute READ SERIAL FLASH DISCOVERY PARAMETER command, S# is driven
LOW. The command code is input on DQ0, followed by three address bytes and eight
dummy clock cycles (address is always 3 bytes, even if the device is configured to work
in 4-byte address mode). The device outputs the information starting from the specified
address. When the 2048-byte boundary is reached, the data output wraps to address 0 of
the serial Flash discovery parameter table. The operation is terminated by driving S#
HIGH at any time during data output.
The operation always executes in continuous mode so the read burst wrap setting in the
volatile configuration register does not apply.
PDF: 09005aef84752721
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN
40
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