MRF39RA Datasheet, PDF (61/72 Pages) Microchip Technology – Low-Power, Integrated UHF Receiver

MRF39RA
7.4.3 RECEIVER
All receiver tests are performed with RxBw = 10 kHz
(Single Side Bandwidth) as programmed in RegRxBw,
receiving a PN15 sequence with a BER of 0.1% (bit
synchronizer is enabled), unless otherwise specified.
The LNA impedance is set to 200 Ohms, by setting bit
LnaZin in RegLna to ‘1’. Blocking tests are performed
with an unmodulated interferer. The wanted signal
power for the blocking immunity, ACR, IIP2, IIP3 and
AMR tests is set 3 dB above the nominal sensitivity
level. Table 7-5 shows the receiver specification.
TABLE 7-5: RECEIVER SPECIFICATION
Symbol
Description
Conditions
Min. Typ. Max. Unit
RFS_F
FSK sensitivity, highest LNA FDA = 5 kHz, BR = 1.2 kbps
—
gain
FDA = 5 kHz, BR = 4.8 kbps
—
FDA = 40 kHz, BR = 38.4 kbps —
-118
-114
-105
FDA = 5 kHz, BR = 1.2 kbps⁽¹⁾ —
-120
RFS_O
OOK sensitivity, highest LNA BR = 4.8 kbps
gain
— -112
CCR
Co-channel rejection
—
-13 -10
ACR
Adjacent channel rejection Offset = +/- 25 kHz
Offset = +/- 50 kHz
— 42
37 42
BI
Blocking immunity
Offset = +/- 1 MHz
— 66
Offset = +/- 2 MHz
— 71
Offset = +/- 10 MHz
— 79
Blocking immunity
Wanted signal at sensitivity
+16 dB
Offset = +/- 1 MHz
Offset = +/- 2 MHz
Offset = +/- 10 MHz
— 62
— 65
— 73
AMR
AM Rejection, AM modulated Offset = +/- 1 MHz
interferer with 100%
Offset = +/- 2 MHz
modulation depth,
Offset = +/- 10 MHz
fm = 1 kHz, square
— 66
— 71
— 79
IIP2
Second order input intercept Lowest LNA gain
— +75
point
Highest LNA gain
— +35
Unwanted tones are 20 MHz
above the LO
IIP3
Third order input intercept Lowest LNA gain
— +20
point
Highest LNA gain
-23 -18
Unwanted tones are 1 MHz
and 1.995 MHz above the
LO
BW_SSB
Single side channel filter BW Programmable
2.6 —
IMR_OOK
Image rejection in OOK
mode
Wanted signal level = -106 dBm 27 30
TS_RE
Receiver wake-up time, from RxBw = 10 kHz, BR = 4.8 kbps — 1.7
PLL locked state to RxReady RxBw = 200 kHz, BR = 100 kbps — 96
TS_RE_AGC
Receiver wake-up time, from RxBw= 10 kHz, BR = 4.8 kbps — 3.0
PLL locked state, AGC
RxBw = 200 kHz, BR = 100 kbps
163
enabled
TS_RE_AGC&AFC Receiver wake-up time, from RxBw= 10 kHz, BR = 4.8 kbs
PLL lock state, AGC and
RxBw = 200 kHz, BR = 100 kbs
AFC enabled
— 4.8
265
Note 1: Set SensitivityBoost in RegTestLna to 0x2D to reduce the noise floor in the receiver.
—
—
—
—
-109
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
500
—
—
—
—
—
dBm
dBm
dBm
dBm
dBm
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dBm
dBm
dBm
dBm
kHz
dB
ms
µs
ms
µs
ms
µs
 2015 Microchip Technology Inc.
DS40001778B-page 61