MRF39RA Datasheet, PDF (17/72 Pages) Microchip Technology – Low-Power, Integrated UHF Receiver

FIGURE 2-8:
BIT SYNCHRONIZER DESCRIPTION
Raw demodulator
output
(FSK or OOK)
MRF39RA
BitSync Output
To pin DATA and
DCLK in Continuous
mode
D ATA
DC LK
To ensure correct operation of the bit synchronizer, the
following conditions must be satisfied:
• A preamble (0x55 or 0xAA) of at least 12 bits is
required for synchronization; the longer the
synchronization, the better the packet success
rate
• The subsequent payload bit stream must have at
least one transition from ‘0’ to ‘1’ or ‘1’ to ‘0’ every
16 bits during data transmission
• The bit rate matching between the transmitter and
the receiver must be better than 6.5%.
2.4.15
FREQUENCY ERROR INDICATOR
(FEI)
This function provides information about the frequency
error of the local oscillator (LO) compared with the
carrier frequency of a modulated signal at the input of
the receiver. When the FEI block is launched, the
frequency error is measured and the signed result is
loaded in FeiValue in RegFei, in two’s complement
format. The time required for an FEI evaluation is four
times the bit period.
To ensure a proper behavior of the FEI:
• The operation must be done during the reception
of preamble
• The sum of the frequency offset and the 20 dB
signal bandwidth must be lower than the base
band filter bandwidth.
The 20 dB bandwidth of the signal (double-side
bandwidth) can be evaluated as shown in Equation 2-8.
EQUATION 2-8: 20 DB BANDWIDTH
B W _{20 d B}
=
2



F_D
E
V
+
B_---2-R_{---}
The frequency error, in Hz, can be calculated with the
formula in Equation 2-9.
EQUATION 2-9: FREQUENCY ERROR-HZ
FEI = F_STEP  FeiValue
FIGURE 2-9:
FEI PROCESS
MRF39RA in Rx mode
Preamble-modulated input signal
Signal level > Sensitivity
Set FeiStart = 1
No
FeiDone = 1
Yes
Read FeiValue
 2015 Microchip Technology Inc.
DS40001778B-page 17